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Information sending method and device and information receiving method and device

專利號
US11528694B2
公開日期
2022-12-13
申請人
ZTE CORPORATION（CN Shenzhen）
發(fā)明人
Xing Liu; Peng Hao; Haigang He; Feng Bi
IPC分類
H04W72/04; H04W56/00; H04W72/00
技術(shù)領(lǐng)域
coreset,ssb,slot,resource,domain,in,symbols,occupies,monitoring,signal
地域： Guangdong

摘要

Information transmission and reception methods and apparatus are disclosed, where the transmission method includes: carrying configuration information of a control resource set on a physical broadcast channel; where the configuration information is used to indicate to a terminal at least one of the following of the control resource set: time domain position information and frequency domain position information; and transmitting the control resource set to the terminal according to the configuration information.

說明書

In a configuration of FIG. 16(7), each CORESET occupies 2 symbols, where a CORESET of the first SSB occupies the first and second symbols in a former slot; a CORESET of the second SSB occupies the third and fourth symbols in the former slot; a CORESET of the third SSB occupies the first and second symbols in a latter slot; a CORESET of the fourth SSB occupies the first and second symbols in a slot outside a 5 ms SSB time window; and ‘time domain spacing between the CORESET of the first SSB and the CORESET of the fourth SSB’ is equal to 5 ms.

In a configuration of FIG. 16(8), each CORESET occupies 2 symbols, where a CORESET of the first SSB occupies the first and second symbols in a former slot; a CORESET of the second SSB occupies the third and fourth symbols in the former slot; a CORESET of the third SSB occupies the first and second symbols in a former slot; a CORESET of the fourth SSB occupies the first and second symbols in a slot outside a 5 ms SSB time window; and ‘time domain spacing between the CORESET of the second SSB and the CORESET of the fourth SSB’ is equal to 5 ms, or ‘time domain spacing between the CORESET of the third SSB and the CORESET of the fourth SSB’ is equal to 5 ms.

In a configuration of FIG. 16(9), each CORESET occupies 1 or 2 or 3 or 4 symbols, a multiplexing manner of FDM is used for CORESETs and corresponding SSBs, that is:

權(quán)利要求

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