It should be noted that a specific connection medium between the communications interface 601, the processor 602, and the memory 603 is not limited in this embodiment of this application. In this embodiment of this application, in FIG. 6, the memory 603, the processor 602, and the communications interface 601 are connected by using a bus. The bus is represented by using a thick line in FIG. 6, and a connection manner between other components is merely used for schematic description, and is not limited thereto. The bus may be classified into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used to represent the bus in FIG. 6, but this does not mean that there is only one bus or only one type of bus.
Based on a same inventive concept, as shown in FIG. 7, an embodiment of this application further provides a communications apparatus 700. The communications apparatus 700 is applied to a network device. The apparatus 700 may be specifically a processor, a chip, a chip system, a functional module, or the like in the network device. The apparatus 700 may include a processing unit 701 and a transceiver unit 702. The processing unit 701 is configured to control and manage an action of the apparatus 700.
