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Joint activation and/or release for multiple configured grant and/or semi-persistent scheduling configurations

專利號(hào)
US11533738B2
公開日期
2022-12-20
申請(qǐng)人
QUALCOMM Incorporated(US CA San Diego)
發(fā)明人
Seyed Ali Akbar Fakoorian; Wei Yang; Jing Sun; Seyedkianoush Hosseini; Xiaoxia Zhang; Mostafa Khoshnevisan
IPC分類
H04W72/12; H04L1/18; H04W72/14; H04W72/04; H04W76/36; H04W80/02; H04W76/11; H04W76/27
技術(shù)領(lǐng)域
sps,cg,ue,dci,or,in,may,downlink,released,uplink
地域: CA CA San Diego

摘要

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a single downlink control information (DCI) message. The UE may map a bit sequence in the single DCI message to a configuration set that includes multiple downlink semi-persistent scheduling configurations or multiple uplink configured grant configurations to be jointly activated or released. Numerous other aspects are provided.

說明書

In a nineteenth aspect, alone or in combination with one or more of the first through eighteenth aspects, the UE may transmit, through a medium access control (MAC) control element, an acknowledgement of the single DCI message based at least in part on the bit sequence indicating that the multiple uplink CG configurations are to be jointly activated or released, and the MAC control element may further indicate an index corresponding to an acknowledged uplink CG configuration and indicate whether the acknowledgement is for a joint activation or a joint release.

In a twentieth aspect, alone or in combination with one or more of the first through nineteenth aspects, the acknowledgement includes a bitmap with a set of bits to jointly acknowledge all of the multiple uplink CG configurations that are to be jointly activated or released.

Although FIG. 4 shows example blocks of process 400, in some aspects, process 400 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 4. Additionally, or alternatively, two or more of the blocks of process 400 may be performed in parallel.

The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the aspects to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the aspects.

As used herein, the term “component” is intended to be broadly construed as hardware, firmware, and/or a combination of hardware and software. As used herein, a processor is implemented in hardware, firmware, and/or a combination of hardware and software.

權(quán)利要求

1
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