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Display panel with internal traces proofed against electromagentic interference

專利號
US11553587B2
公開日期
2023-01-10
申請人
JADARD TECHNOLOGY INC.（CN Shenzhen）
發(fā)明人
Yi-Wei Hung; Gang Liu
IPC分類
H05K1/02
技術(shù)領(lǐng)域
trace,traces,grounding,power,display,p2,region,p3,p1,in
地域： Shenzhen

摘要

A display panel with display and non-display regions has pixel units in the display region. The non-display region defines a bonding region in which there are traces and driving chips. The driving chips are bonded in a flexible printed circuit, and electrically connect with the pixel units. The traces include high-speed signal traces, power traces, and grounding traces. The grounding traces are adjacent to the power traces and so disposed as to shield against electromagnetic interference affecting the signal and power traces, the grounding traces serving as reference ground to the power traces, and form a shield against electromagnetic interference.

說明書

1 2 3 4 5 6 7 8 9 10 11
FIELD OF THE INVENTION

The subject matter herein generally relates to display panels.

BACKGROUND

Display panels are widely used in electronic devices, such as notebooks, mobile phones, personal digital assistants (PDAs), digital cameras, and wearable devices, as user interfaces. The display panel defines a display region and a non-display region surrounding with the display region. In the non-display region, there are driving chips on an array substrate, such as a source driver, a gate driver, and a time controller. A flexible printed circuit (FPC) with several signal traces is used for transmitting signals between the driving chips and the array substrate. The FPC is bonded on the array substrate in a chip-on-flex (COF) manner. The signal traces can be different types, such as high-speed signal traces, low-speed signal traces, power traces, and so on. The adjacent high-speed signal trace may be seen as a reference trace by the power trace, which can cause fluctuations in the signals on the high-speed signal trace. Electromagnetic interference from external electronic devices can also affect the signals of the high-speed signal trace and the power trace, reducing display performance of the display panel.

There is room for improvement in the art.

BRIEF DESCRIPTION OF THE FIGURES

Implementations of the present disclosure will now be described, by way of example only, with reference to the attached figures.

FIG. 1 is a diagram illustrating an embodiment of an electronic device with a display panel.

權(quán)利要求

1
What is claimed is:1. A display panel, the display panel defines a display region and a non-display region; the non-display region defines a bonding region, the bonding region comprising:several traces; anddriving chips bonded on a flexible printed circuit (FPC), and electrically connect to the traces;wherein the traces comprises high-speed signal traces, power traces, and grounding traces; the high-speed traces provide high-speed signal from the driving chip to the display region; the power traces provide power signal to the display panel; the grounding traces are disposed adjacent to the power traces; the grounding traces serve as reference grounds to the power traces, and form an electromagnetic shielding path; andwherein the power traces comprise a first power trace with a first specified width, a two second power traces with a second specified trace, and a third power trace with a third specified trace width, the high-speed signal trace is disposed between the second power trace adjacent to the first power trace and the third power trace.2. The display panel of claim 1, wherein the first, second, and third specified widths of the first, second and third traces, respectively, are each different from the other.3. The display panel of claim 2, wherein there are two grounding traces; one of the second power trace is disposed between the first power trace and the high-speed signal traces, and another second power trace is disposed on an edge of the bonding region adjacent to the display region, and is adjacent to the third power trace; the high-speed signal traces are disposed between the second power trace adjacent to the first power trace and the third power trace; one of the grounding traces is disposed between the second power trace adjacent to the first power trace and the high-speed signal trace, and serves as the reference ground to the first power trace and the second power trace; the other grounding trace is disposed between the second power trace adjacent to the display region and the third power trace, and serves as the reference ground to the second power trace and the third power trace.4. The display panel of claim 3, wherein the first power trace is disposed on an edge of the bonding region away from the display region.5. The display panel of claim 2, wherein there are three grounding traces; the two second power traces sandwiches the first power trace, the third power trace, and the high-speed signal trace; one of the grounding traces is disposed outside the second power trace away from the display region, and serves as the reference ground to the second power trace away from the display region; one of the three grounding traces is disposed outside of the second power trace adjacent to the display region and the third power trace, and serves as the reference ground to the second power trace adjacent to the display region; one of the three grounding traces is disposed between the first power trace and the third power trace, and serves as a reference ground to the first power trace and the third power trace.6. The display panel of claim 5, wherein the first power trace is sandwiched between the third power trace and the second power trace adjacent to the display region.7. The display panel of claim 1, wherein the traces are spaced from each other in a specified distance; the specified distance is 15 μm.8. The display panel of claim 1, wherein a range of the width of the grounding trace is from 10 μm to 2.35 mm.9. The display panel of claim 1, wherein the width of the grounding trace is 20 μm.10. The display panel of claim 1, wherein the width of the grounding trace is 10 μm.
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