The traces b-W include several power traces b-P, several high-speed signal traces b-S, and several connection pins b-Pin. The traces b-W are spaced from each other by a specified distance K1. In one embodiment, the specified distance K1 is 15 μm. The power traces b-P include at least one first power trace P1 with a first specified trace width, at least two second power trace b-P2 with a second specified trace width, and at least one third power trace b-P3 with a third specified trace width. The first power trace b-P1, the second power traces b-P2, and the third power trace b-P3 transmit different power voltages, and the first specified trace width, the second specified trace width, and the third specified trace width are different from each other. In one embodiment, the power traces b-W include a first power trace b-P1, two second power traces b-P2, and a third power trace b-P3. The second power traces b-P2 sandwich the first power trace b-P1, the third power trace b-P3, and the high-speed signal trace b-S. The high-speed signal traces b-S are disposed between the second power trace b-P2 away from the display region 101 and the third power trace b-P3. The first power trace b-P1 is disposed between the third power trace b-P3 and the second power trace b-P2 adjacent to the display region 101.