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Backplane footprint for high speed, high density electrical connectors

專利號
US11553589B2
公開日期
2023-01-10
申請人
Amphenol Corporation(US CT Wallingford)
發(fā)明人
Marc Robert Charbonneau; Jose Ricardo Paniagua
IPC分類
H05K1/02; H05K1/03; H05K1/09; H05K1/11; H05K1/18; H05K3/04; H05K3/30; H05K3/32; H05K3/40; H05K3/42; H05K3/46; H01R12/51; H01R12/70; H01R12/73; H01R12/71
技術(shù)領(lǐng)域
vias,antipad,shadow,backplane,conductive,connector,signal,in,ground,layers
地域: CT CT Wallingford

摘要

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.

說明書

As indicated above, the shadow vias 560 and 562 are located between signal vias 530 and 532. As shown in FIG. 5B, shadow vias 560 and 562 are located on a first line 570 that is perpendicular to a second line 572 that passes through signal vias 530 and 532 in a direction of the columns 500, 502. The first line 570 may be located midway between signal vias 530 and 532, such that the shadow vias 560 and 562 are equally spaced from signal vias 530 and 532. In addition, the shadow vias 560 and 562 may at least partially overlap the edges of antipad 542, thus effectively electrically shorting opposite sides of antipad 542 between signal vias 530 and 532 and dividing antipad 542 into two separate antipad sections respectively surrounding signal vias 530 and 532.

The shadow vias 560 and 562 include pads 564 and 566, respectively. In some embodiments, the pads of the shadow vias 560 and 562 physically and electrically contact each other, while in other embodiments the pads of the shadow vias 560 and 562 are spaced apart and do not contact each other.

In the example of FIG. 5A, each of via patterns 520, 522, 524 and 526 includes two shadow vias located between the signal vias of each differential signal pair. In further embodiments, each via pattern may include a single shadow via located between the signal vias or more than two shadow vias. Furthermore, the shadow vias may be implemented as one or more circular shadow vias or one or more slot-shaped shadow vias.

權(quán)利要求

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