This problem is strongly accentuated for transistors with fast switching capabilities, such as Gallium Nitride (GaN) and Silicon Carbide Metal-Oxide-Semiconductor (SiCMOS) transistors. When multiple transistors are placed in parallel, the switching performance of the set of transistors is strongly affected by the presence of unequal parasitic elements for each transistor, more specifically parasitic leakage inductance.

Considering a transistor designed and manufactured by a given manufacturer, the transistor already integrates (at die level) many transistor cells in parallel, to achieve a given electrical current capacity for the transistor. Since the surface covered by these multiple cells in parallel is very small, electrical current sharing is well controlled at the transistor level. However, when several of these transistors are used in parallel, it is difficult to avoid the aforementioned issues occurring during the switching periods of the parallel transistors. This is due to the fact that the internal cells of each respective transistor are separated by the external connectivity of the transistors (e.g. pins, printed circuit traces, etc.) and the influence of this external connectivity on electrical current sharing is not easy to predict if it is not well designed.

Therefore, there is a need for a new printed circuit board comprising a plurality of power transistor switching cells in parallel.