The transistor leg (comprising the power transistors 100 and 200 in series) and its associated decoupling capacitor(s) 500 are placed as close as possible to one another, in order to minimize the parasitic elements influencing the switching dynamic of the power transistors 100 and 200.

Details of the implementation of the gate driver circuit 400 are not provided, because such gate driver circuits are well known in the art and the precise implementation of the gate driver circuit 400 is not within the scope of the present disclosure. An exemplary implementation has been detailed previously, in relation to FIG. 2. Furthermore, tables 1 and 2 describe the logic applied by the gate driver circuit 400 for controlling and synchronizing the power transistors 100 and 200 under its control.

A controller 50 generates and transmits the electrical control signal 431 for controlling the gate driver circuit 400. In a common implementation, the gate driver circuit 400 amplifies the electrical control signal 431 received from the controller 50. The gate driver circuit 400 generates (based on the amplified electrical control signal 431) the respective adequate electrical voltages applied to the respective gates G of each power transistor (100, 200). The gate driver circuit 400 also provides galvanic isolation between the power side (the power transistors 100 and 200) and the control side (the controller 50).