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Initiating random access in a target cell in a non-terrestrial network

專利號
US11617215B2
公開日期
2023-03-28
申請人
QUALCOMM Incorporated（US CA San Diego）
發(fā)明人
Bharat Shrestha; Umesh Phuyal; Ayan Sengupta; Alberto Rico Alvarino; Liangping Ma; Xiao Feng Wang
IPC分類
H04W56/00; H04W74/08; H04W74/00; H04W36/00; H04W24/08; H04W84/06
技術(shù)領(lǐng)域
rach,ue,cell,target,or,in,may,ues,procedure,station
地域： CA CA San Diego

摘要

Various aspects described herein relate to dynamically controlling a time when random access initiated in a target cell of a non-terrestrial network. For example, when a user equipment (UE) detects an event that triggers a random access procedure in the target cell, the UE may monitor a control channel from the target cell for a control signal during a target cell monitoring window prior to initiating random access in the target cell. For example, the control signal may include a dynamic indication to identify UEs allowed to initiate random access, whereby a UE is not permitted to autonomously start contention-based random access in the target cell during the target cell monitoring window unless the UE has received the control signal. In this way, the target cell may regulate a rate at which UEs initiate the RACH procedure in order to manage congestion in the target cell.

說明書

The number and arrangement of components shown in FIG. 9 are provided as an example. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in FIG. 9. Furthermore, two or more components shown in FIG. 9 may be implemented within a single component, or a single component shown in FIG. 9 may be implemented as multiple, distributed components. Additionally, or alternatively, a set of (one or more) components shown in FIG. 9 may perform one or more functions described as being performed by another set of components shown in FIG. 9.

FIG. 10 is a diagram illustrating an example 1000 of a hardware implementation for an apparatus 1005 employing a processing system 1010. The apparatus 1005 may be a UE.

The processing system 1010 may be implemented with a bus architecture, represented generally by the bus 1015. The bus 1015 may include any number of interconnecting buses and bridges depending on the specific application of the processing system 1010 and the overall design constraints. The bus 1015 links together various circuits including one or more processors and/or hardware components, represented by the processor 1020, the illustrated components, and the computer-readable medium/memory 1025. The bus 1015 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and/or power management circuits.

權(quán)利要求

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