A terminal 44 and a wiring 42 shown in FIG. 4 are conductor patterns formed on a surface 41A (see FIG. 5) of a core insulating layer 41 (see FIG. 5) composing the substrate FPC1. Here, as shown in FIG. 5, the surface 41A of the core insulating layer 41 has a connection region 40C1 facing the substrate PCB1, and the surface 41B of the core insulating layer 41 has a connection region 40C2 overlapping the connection region 40C1. Although the terminal 44 and the wiring 42 are formed so as to be integral with each other, they are distinguished and defined herein as follows. That is, among the conductor patterns formed on the surface 41A of the core insulating layer 41 and electrically connected to the substrate PCB1, a portion located at the connection region 40C1 in which a solder resist film SR1 is formed is the terminal 44. On the other hand, among the conductor patterns formed on the surface 41A of the core insulating layer 41 and electrically connected to the substrate PCB1, a portion located at a position other than the connection region 40C1 is the wiring 42. A plurality of the wirings 42 is covered by a protective insulating film (plastic film, insulating film, protective film) PF1.