As shown in FIG. 4, the plurality of terminals 44 includes a signal terminal 44s1 to which an electrical signal is transmitted, and a reference potential terminal 44g1 electrically connected to the wiring 43 to which a reference potential is supplied. As shown in FIG. 5, in a cross-sectional view, the wiring 43 overlaps a signal wiring 42s1 electrically connected to the signal terminal 44s1 among the plurality of wirings 42, and is arranged along an extension direction of the signal wiring 42s1. The signal terminal 44s1 and the signal wiring 42s1 are included in a transmission path electrically connecting the semiconductor device 10 and the semiconductor device 20 shown in FIG. 2 to each other. In addition, as shown in FIG. 6, the plurality of terminals 45 and the plurality of terminals 44 are respectively and electrically connected via a plurality of via wirings 46. The plurality of terminals 45 includes a signal terminal (backside signal terminal) 45s1 formed at a position overlapping the signal terminal 44s1 and electrically connected to the signal terminal 44s1 via a via wiring 46s1, and a reference potential terminal (backside reference potential terminal) 45g1 formed at a position overlapping the reference potential terminal 44g1 and electrically connected to the signal terminal 44g1 via a via wiring 46g1. As shown in FIG. 3, the reference potential terminal (backside reference potential terminal) 45g1 is also electrically connected to the wiring 43. In addition, in the example shown in FIG. 6, the plurality of terminals 45 includes a signal terminal (backside signal terminal) 45s2 formed at a position overlapping a signal terminal 44s2 and electrically connected to the signal terminal 44s2 via a via wiring 46s2.