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Electronic device

專利號
US11617265B1
公開日期
2023-03-28
申請人
RENESAS ELECTRONICS CORPORATION(JP Tokyo)
發(fā)明人
Kazuaki Tsuchiyama; Tatsuaki Tsukuda
IPC分類
H05K1/11; H05K1/14; H01L23/538; H01L25/065
技術(shù)領(lǐng)域
fpc1,terminal,wiring,44s1,signal,pcb1,substrate,in,terminals,44g1
地域: Tokyo

摘要

A width of each of a first signal terminal and a reference potential terminal formed in a first connection region of a core insulating layer constituting a flexible substrate is larger than a width of each of a first backside signal terminal and a backside reference potential terminal formed in a second connection region of the core insulating layer. In addition, a first separation distance between the first signal terminal and the reference potential terminal arranged adjacent to the first signal terminal is smaller than a second separation distance between the first backside signal terminal and the backside reference potential terminal arranged adjacent to the first backside signal terminal. An insulating film formed on a first surface of the core insulating layer at a position overlapping each of the first connection region and the second connection region covers the first connection region such that the second connection region is exposed.

說明書

Note that, as shown in FIG. 6, each of the via wirings 46 is formed by depositing a metal film along a wall surface of a via hole 47 formed so as to penetrate the core insulating layer 41 from one of the surface 41A and the surface 41B to the other of the surface 41A and the surface 41B. Therefore, a through hole (portion of the via hole 47) remains in a center of the via wiring 46 formed in the via hole 47. For example, in a case where a solder material is used as the conductive joint material SB and the amount of the applied solder material is large, the solder material can creep up to the terminal 45 on the surface 41B side via the through hole which is a portion of the via hole 47. Each of the terminals 45 is not covered by the solder resist film SR1. Therefore, in a case where the solder material creeps up to the surface 41B side (that is, the connection region 40C2 side) and the separation distance between the terminals 45 is short, short-circuiting can occur in adjacent terminals 45 via the solder material.

In the case of the present embodiment, the separation distance (such as the separation distance 45GP1) between each of the terminals 45 is larger than the separation distance 44GP1 between the signal terminal 44s1 and the reference potential terminal 44g1. Therefore, even in a case where the conductive joint material SB which is a solder material goes around to the connection region 40C2 side, short-circuiting in the signal terminal 44s1 and the reference potential terminal 44g1 via the solder material can be prevented.

權(quán)利要求

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