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Chroma quantization in video coding

專利號(hào)
US11659182B2
公開日期
2023-05-23
申請(qǐng)人
Apple Inc.（US CA Cupertino）
發(fā)明人
Alexandros Tourapis; Guy Cote
IPC分類
H04N19/124; H04N19/30; H04N19/70; H04N19/126; H04N19/186; H04N19/157; H04N19/86; H04N19/136; H04N19/13; H04N19/15; H04N19/159; H04N19/51; H04N19/61; H04N19/96; H04N19/172; H04N19/176
技術(shù)領(lǐng)域
chroma,qp,offset,luma,qg,offsets,picture,values,coding,qgs
地域： CA CA Cupertino

摘要

A method of signaling additional chroma QP offset values that are specific to quantization groups is provided, in which each quantization group explicitly specifies its own set of chroma QP offset values. Alternatively, a table of possible sets of chroma QP offset values is specified in the header area of the picture, and each quantization group uses an index to select an entry from the table for determining its own set of chroma QP offset values. The quantization group specific chroma QP offset values are then used to determine the chroma QP values for blocks within the quantization group in addition to chroma QP offset values already specified for higher levels of the video coding hierarchy.

說(shuō)明書

FIG. 20 conceptually illustrates an electronic system 2000 with which some embodiments of the invention are implemented. The electronic system 2000 may be a computer (e.g., a desktop computer, personal computer, tablet computer, etc.), phone, PDA, or any other sort of electronic device. Such an electronic system includes various types of computer readable media and interfaces for various other types of computer readable media. Electronic system 2000 includes a bus 2005, processing unit(s) 2010, a graphics processing unit (GPU) 2015, a system memory 2020, a network 2025, a read-only memory 2030, a permanent storage device 2035, input devices 2040, and output devices 2045.

The bus 2005 collectively represents all system, peripheral, and chipset buses that communicatively connect the numerous internal devices of the electronic system 2000. For instance, the bus 2005 communicatively connects the processing unit(s) 2010 with the read-only memory 2030, the GPU 2015, the system memory 2020, and the permanent storage device 2035.

From these various memory units, the processing unit(s) 2010 retrieves instructions to execute and data to process in order to execute the processes of the invention. The processing unit(s) may be a single processor or a multi-core processor in different embodiments. Some instructions are passed to and executed by the GPU 2015. The GPU 2015 can offload various computations or complement the image processing provided by the processing unit(s) 2010.

權(quán)利要求

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