FIG. 17 is a block diagram illustrating an example of the architecture for a computer system or other control device 1700 that can be utilized to implement various portions of the presently disclosed technology, including (but not limited to) method 1300 and method 1400. In FIG. 17, the computer system 1700 includes one or more processors 1705 and memory 1710 connected via an interconnect 1725. The interconnect 1725 may represent any one or more separate physical buses, point to point connections, or both, connected by appropriate bridges, adapters, or controllers. The interconnect 1725, therefore, may include, for example, a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), IIC (I2C) bus, or an Institute of Electrical and Electronics Engineers (IEEE) standard 674 bus, sometimes referred to as “Firewire.”

The processor(s) 1705 may include central processing units (CPUs) to control the overall operation of, for example, the host computer. In certain embodiments, the processor(s) 1705 accomplish this by executing software or firmware stored in memory 1710. The processor(s) 1705 may be, or may include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.