Single well one transistor and one capacitor nonvolatile memory device and integration schemes
地域：
Singapore
摘要
A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.
說(shuō)明書
The disclosed embodiments relate generally to nonvolatile memory devices, and more particularly, to nonvolatile memory devices with high density, a compact size and improved reliability.
A nonvolatile memory device retains stored data even if power is turned off. An example of a nonvolatile memory device includes electrically erasable programmable read only memory (EEPROM) and flash EEPROM. In typical flash memory architecture, a floating gate may be used to store charges. The floating gate may be arranged over an active region such as a p-well. A source region may be formed in the p-well adjacent to a first side of the floating gate and a drain region may be formed in the p-well adjacent to a second side of the floating gate. An n-well capacitor adjacent to the floating gate may be used to bias the floating gate. The n-well capacitor may comprise a polysilicon layer over an n-well and a highly doped n+ region as an input terminal. An isolation structure may separate the n-well from an adjacent p-well.
權(quán)利要求
What is claimed:1. A nonvolatile memory device comprising:an active region surrounded by an isolation structure; a floating gate having a first end, a second end opposite to the first end, a middle portion between the first end and the second end, a first side adjacent to the middle portion and a second side opposite to the first side, wherein the middle portion is over the active region, and the first end and the second end of the floating gate are over the isolation structure; a dielectric layer between the floating gate and the active region, wherein at least a portion of the dielectric layer is over the isolation structure; a first doped region in the active region adjacent to the first side of the floating gate and a second doped region in the active region adjacent to the second side of the floating gate; a first capacitor over the floating gate, the first capacitor comprising a first electrode and a second electrode, and a capacitor dielectric between the first electrode and the second electrode, wherein the first electrode of the first capacitor is electrically coupled to the floating gate; and contacts arranged over the first doped region, the second doped region and the second electrode of the first capacitor, wherein the contacts couple the first doped region, the second doped region and the second electrode of the first capacitor to input terminals. 2. The nonvolatile memory device of claim 1 , wherein an area of the first capacitor is at least equal to an area of the floating gate. 3. The nonvolatile memory device of claim 1 , wherein an area of the first capacitor is larger than an area of the floating gate. 4. The nonvolatile memory device of claim 1 further comprising:a second capacitor, wherein a first electrode of the second capacitor is directly above the isolation structure and adjacent to the floating gate. 5. The nonvolatile memory device of claim 4 , wherein a second electrode of the second capacitor comprises the floating gate. 6. The nonvolatile memory device of claim 5 further comprising:a spacer dielectric between the first electrode of the second capacitor and the second electrode of the second capacitor. 7. The nonvolatile memory device of claim 4 , wherein the first capacitor partially overlaps with the first electrode of the second capacitor. 8. The nonvolatile memory device of claim 7 further comprising:an insulating layer separating the first capacitor from the first electrode of the second capacitor. 9. The nonvolatile memory device of claim 1 , wherein the active region comprises a p-well region. 10. The nonvolatile memory device of claim 1 , wherein the first doped region is a source region and the second doped region is a drain region. 11. An array of nonvolatile memory devices comprising:a first active region, a second active region and an isolation structure surrounding each active region, wherein a portion of the isolation structure is between the first active region and the second active region; a first array of floating gates and a second array of floating gates, each floating gate having a first end, a second end opposite to the first end, a middle portion between the first end and the second end, a first side adjacent to the middle portion and a second side opposite to the first side, wherein the middle portion of each floating gate from the first array is arranged over the first active region, the middle portion of each floating gate from the second array is arranged over the second active region, and the first end and the second end of each floating gate are over the isolation structure; a dielectric layer between each floating gate from the first array and the first active region, and between each floating gate from the second array and the second active region, wherein at least a portion of the dielectric layer is over the isolation structure; a first doped region in each active region adjacent to the first side of each floating gate and a second doped region in each active region adjacent to the second side of each floating gate; and a first capacitor over each floating gate, the first capacitor comprising a first electrode and a second electrode, and a capacitor dielectric between the first electrode and the second electrode, wherein the first electrode of the first capacitor is electrically coupled to each floating gate; and contacts arranged over the first doped region, the second doped region and the second electrode of the first capacitor, wherein the contacts couple the first doped region, the second doped region and the second electrode of the first capacitor to input terminals. 12. The array of nonvolatile memory devices of claim 11 , wherein an area of the first capacitor is at least equal to an area of each floating gate. 13. The array of nonvolatile memory devices of claim 11 further comprising:a second capacitor, wherein a first electrode of the second capacitor is arranged over the portion of the isolation structure between the first active region and the second active region and is adjacent to the floating gates. 14. A method of fabricating a nonvolatile memory device comprising:forming an active region surrounded by an isolation structure; forming a floating gate having a first end, a second end opposite to the first end, a middle portion between the first end and the second end, a first side adjacent to the middle portion and a second side opposite to the first side, wherein the middle portion of the floating gate is over the active region, and the first end and the second end of the floating gate are over the isolation structure; forming a dielectric layer between the floating gate and the active region, wherein at least a portion of the dielectric layer is over the isolation structure; forming a first doped region in the active region adjacent to the first side of the floating gate; forming a second doped region in the active region adjacent to the second side of the floating gate; forming a first capacitor over the floating gate, the first capacitor comprising a first electrode and a second electrode, and a capacitor dielectric between the first electrode and the second electrode, wherein the first electrode of the first capacitor is electrically coupled to the floating gate; and forming contacts over the first doped region, the second doped region and the second electrode of the first capacitor, wherein the contacts couple the first doped region, the second doped region and the second electrode of the first capacitor to input terminals. 15. The method of claim 14 , wherein forming the active region surrounded by the isolation structure further comprises:forming an isolation structure in a substrate; and forming the active region in the substrate, wherein the active region is surrounded by the isolation structure. 16. The method of claim 14 , wherein forming the floating gate further comprises:forming a polysilicon layer over the active region and over the isolation structure; and patterning the polysilicon layer to form the floating gate having the first end, the second end opposite to the first end, and the middle portion between the first end and the second end, wherein the middle portion is over the active region, and the first end and the second end of the floating gate are over the isolation structure. 17. The method of claim 16 further comprising:patterning the polysilicon layer to form a first electrode of a second capacitor adjacent to the floating gate and over the isolation structure. 18. The method of claim 17 further comprising:forming a spacer dielectric adjacent to a sidewall of the floating gate and to a sidewall of the first electrode of the second capacitor. 19. The method of claim 14 , wherein forming the first capacitor further comprises:forming an insulating layer over the active region, over the floating gate and over the isolation structure; forming a contact pillar in the insulating layer over the floating gate; and forming the first electrode of the first capacitor over the contact pillar and over the insulating layer. 20. The nonvolatile memory device of claim 1 , wherein the first end and the second end of the floating gate are directly above the isolation structure.
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