Single well one transistor and one capacitor nonvolatile memory device and integration schemes
地域：
Singapore
摘要
A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.
說明書
Erasing may be by hot hole injection. For example, during erase, a negative voltage of approximately ?2.5V may be applied to the first capacitor 168 to bias the floating gate 112. A suitable voltage of approximately 6 to 8V may be applied to the drain 108. The source 106 and the substrate terminal 116 may be grounded. Hot holes may be generated in the channel region and injected into the floating gate 112 to recombine with the electrons stored in the floating gate 112. The memory device array 100 may be erased simultaneously.
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