FIG. 5 is a cross-section view of a partially completed nonvolatile memory device array 100 taken along section line A-A′ of FIG. 1A after formation of a source region 106, a drain region 108 and a substrate contact 116, according to an embodiment of the disclosure. Referring to FIG. 5, the source 106 and the drain 108 regions may be formed by doping an upper surface of the active regions 110a and 110b with a suitable dopant such as phosphorus (P), arsenic (As) or antimony (Sb) to form an n⁺ doped region adjacent to a first side of the first floating gate 112a and the second floating gate 112b and to a second side of the first floating gate 112a and the second floating gate 112b opposite to the first side, respectively. The substrate contact 116 may be formed by doping an upper surface of the first active region 110a or the second active region 110b with a suitable dopant, for example boron (B) or boron fluoride (BF₂) to form a p⁺ doped region adjacent to an isolation structure 118.