FIG. 8 is a cross-section view of a partially completed nonvolatile memory device array 200 taken along section line E-E′ of FIG. 2A after formation of a dielectric layer 102, a first floating gate 112a, a second floating gate 112b, a first electrode 208 of a second capacitor and a spacer dielectric 210, according to an embodiment of the disclosure. The formation of the dielectric layer 102 may include depositing a layer of suitable dielectric material, for example silicon dioxide, over the first active region 110a, over the second active region 110b and over the isolation structure 218. A layer of polysilicon may be deposited over the silicon dioxide layer followed by doping with a suitable n-type dopant, for example phosphorus. The doped polysilicon layer and the silicon dioxide layer may be patterned by a conventional photoresist process followed by a wet etch or dry etch to form the first floating gate 112a, the second floating gate 112b, the first electrode 208 of the second capacitor between the first floating gate 112a and the second floating gate 112b and the dielectric layer 102, respectively. The formation of the first floating gate 112a, the second floating gate 112b and the first electrode 208 of the second capacitor between the first floating gate 112a and the second floating gate 112b may be done in the same process and from the same doped polysilicon layer.