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Single well one transistor and one capacitor nonvolatile memory device and integration schemes

專(zhuān)利號(hào)
US11659709B2
公開(kāi)日期
2023-05-23
申請(qǐng)人
GLOBALFOUNDRIES Singapore Pte. Ltd.（SG Singapore）
發(fā)明人
Xinshu Cai; Shyue Seng Tan; Juan Boon Tan; Kiok Boone Elgin Quek; Eng Huat Toh
IPC分類(lèi)
H01L27/11521; H01L29/66; H01L49/02; H01L29/788; H01L29/06
技術(shù)領(lǐng)域
floating,gate,capacitor,112a,112b,region,first,active,110a,dielectric
地域： Singapore

摘要

A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.

說(shuō)明書(shū)

In yet another aspect of the present disclosure, a method of fabricating a nonvolatile memory device is provided. The method comprises providing an active region surrounded by an isolation structure. A floating gate may be provided over the active region, whereby a first end and a second end of the floating gate are over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate.

Numerous advantages may be derived from the embodiments described below. The embodiments provide a compact nonvolatile memory device with a high coupling ratio, a high density and improved reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosed embodiments will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawings:

FIG. 1A is a top view of a nonvolatile memory device array, according to an embodiment of the disclosure.

FIG. 1B is a cross-section view of a nonvolatile memory device array taken along section line B-B′ of FIG. 1A, according to an embodiment of the disclosure.

FIG. 1C is a simplified schematic view of a nonvolatile memory device along section line C-C′ of FIG. 1A, according to an embodiment of the disclosure.

權(quán)利要求

1
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