Semiconductor devices including a contact structure that contacts a dummy channel structure
地域：
Suwon-si
摘要
Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.
說(shuō)明書(shū)
The present application is a continuation application of U.S. patent application Ser. No. 16/451,385, filed on Jun. 25, 2019, now U.S. Pat. No. 11,145,669, which claims priority under 35 U.S.C. § 119 to and the benefit of Korean Patent Application No. 10-2018-0158769, filed on Dec. 11, 2018, in the Korean Intellectual Property Office (KIPO), the entire contents of each of which are hereby incorporated by reference.
The present disclosure relates to semiconductor devices having a contact structure.
As semiconductor devices are becoming highly integrated, the number of electrode layers stacked in a stacked structure is gradually increasing. Each of the plurality of electrode layers may be electrically connected to an element/structure that is outside of the stacked structure through a contact plug. A plurality of contact plugs having a high aspect ratio may make it difficult for the semiconductor devices to be highly integrated.
Example embodiments of the inventive concepts are directed to providing a semiconductor device which is advantageous for high integration while preventing/inhibiting a leakage current and a method of forming the same.
權(quán)利要求
What is claimed is:1. A semiconductor device comprising:a substrate having a cell region and a connection region adjacent to the cell region; a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate; a source mold layer between the substrate and the stacked structure in the connection region; an alternate conductive line between the substrate and the stacked structure in the cell region; a plurality of cell channel structures in the cell region, the plurality of cell channel structures extending into the alternate conductive line while passing through the stacked structure; a plurality of dummy channel structures in the connection region, the plurality of dummy channel structures extending into the source mold layer while passing through the stacked structure; and a contact structure that is among the plurality of dummy channel structures in the connection region while being in direct contact with one of the plurality of electrode layers, wherein each of the plurality of cell channel structures comprises:a channel pattern, and an information storage pattern outside the channel pattern, wherein the channel pattern is electrically connected to the alternate conductive line, wherein each of the plurality of dummy channel structures comprises:a dummy channel pattern, and a dummy information storage pattern outside the dummy channel pattern, wherein the dummy channel pattern is not electrically connected to the alternate conductive line. 2. The semiconductor device according to claim 1 ,wherein the alternate conductive line is at a level substantially equal to that of the source mold layer, and wherein the channel pattern passes through the alternate conductive line and has a lower surface that is below a lower surface of the alternate conductive line. 3. The semiconductor device according to claim 1 ,wherein the alternate conductive line has a thickness substantially equal to that of the source mold layer, and wherein the channel pattern is between spaced-apart portions of the alternate conductive line. 4. The semiconductor device according to claim 1 , wherein the alternate conductive line is in direct contact with the channel pattern while passing through a side surface of the information storage pattern. 5. The semiconductor device according to claim 1 , further comprising:a first portion that is between the alternate conductive line and the stacked structure; and a second portion that is between the substrate and the stacked structure and extends from the first portion, wherein the second portion is in direct contact with side surfaces of the alternate conductive line and the source mold layer. 6. The semiconductor device according to claim 5 , wherein the second portion extends between the alternate conductive line and the source mold layer. 7. The semiconductor device according to claim 6 , wherein the second portion protrudes toward the substrate. 8. The semiconductor device according to claim 1 , wherein the contact structure is in direct contact with at least one of the plurality of dummy channel structures adjacent thereto. 9. The semiconductor device according to claim 1 , wherein the contact structure comprises:a contact plug; and a contact spacer surrounding an outer side of the contact plug. 10. The semiconductor device according to claim 1 , wherein:a width of an upper region of the contact structure is greater than that of a lower region of the contact structure; the upper region of the contact structure is in direct contact with at least one of the plurality of dummy channel structures adjacent thereto; and the lower region of the contact structure is spaced apart from the at least one of the plurality of dummy channel structures adjacent thereto. 11. The semiconductor device according to claim 1 , wherein the contact structure is in direct contact with four of the plurality of dummy channel structures that are spaced apart from one another. 12. The semiconductor device according to claim 1 , wherein the contact structure comprises a protrusion penetrating into one of the plurality of dummy channel structures adjacent thereto. 13. The semiconductor device according to claim 12 , wherein the protrusion overlaps with a center of the one of the plurality of dummy channel structures. 14. The semiconductor device according to claim 1 , wherein the contact structure is in direct contact with the dummy channel pattern and the dummy information storage pattern. 15. The semiconductor device according to claim 1 , wherein:each of the plurality of cell channel structures further comprises a core pattern; each of the plurality of dummy channel structures further comprises a dummy core pattern; the dummy channel pattern is outside the dummy core pattern; and the contact structure passes through the dummy information storage pattern and the dummy channel pattern to be in direct contact with the dummy core pattern. 16. The semiconductor device according to claim 1 , wherein:the information storage pattern comprisesa tunnel insulation layer outside the channel pattern, a charge storage layer outside the tunnel insulation layer, and a blocking layer outside the charge storage layer; and the dummy information storage pattern comprisesa dummy tunnel insulation layer outside the dummy channel pattern, a dummy charge storage layer outside the dummy tunnel insulation layer, and a dummy blocking layer outside the dummy charge storage layer. 17. The semiconductor device according to claim 1 , further comprising:an interlayer insulating layer in the connection region, wherein each of the plurality of electrode layers comprises a pad portion extending into the connection region, wherein the interlayer insulating layer is on the pad portion, wherein the contact structure passes through the interlayer insulating layer to be in direct contact with the pad portion. 18. The semiconductor device according to claim 17 , wherein one of the plurality of dummy channel structures adjacent to the contact structure passes through the pad portion. 19. A semiconductor device comprising:a substrate having a cell region and a connection region adjacent to the cell region; a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate; a source mold layer between the substrate and the stacked structure in the connection region; an alternate conductive line between the substrate and the stacked structure in the cell region; a plurality of cell channel structures in the cell region, the plurality of cell channel structures extending into the alternate conductive line while passing through the stacked structure; a plurality of dummy channel structures in the connection region, the plurality of dummy channel structures extending into the source mold layer while passing through the stacked structure; and a contact structure that is among the plurality of dummy channel structures in the connection region while being in direct contact with one of the plurality of electrode layers, wherein each of the plurality of cell channel structures comprises a channel pattern electrically connected to the alternate conductive line, wherein each of the plurality of dummy channel structures comprises a dummy channel pattern, wherein the dummy channel pattern is not electrically connected to the alternate conductive line. 20. A semiconductor device comprising:a substrate having a cell region and a connection region adjacent to the cell region; a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate; a source mold layer between the substrate and the stacked structure in the connection region; an alternate conductive line between the substrate and the stacked structure in the cell region; a plurality of cell channel structures in the cell region, wherein the alternate conductive line is on opposite sidewalls of each of the plurality of cell channel structures; a plurality of dummy channel structures in the connection region, the plurality of dummy channel structures extending into the source mold layer while passing through the stacked structure; and a contact structure that is among the plurality of dummy channel structures in the connection region while being in direct contact with one of the plurality of electrode layers, wherein each of the plurality of cell channel structures comprises a channel pattern electrically connected to the alternate conductive line, wherein each of the plurality of dummy channel structures comprises a dummy channel pattern, wherein the dummy channel pattern is not electrically connected to the alternate conductive line.
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