FIG. 2A illustrates a three-dimensional (3D) view of a bit-cell comprising a planar transistor and an FE capacitor with templating or texturing layer, in accordance with some embodiments.
FIG. 2B illustrates a 3D view of a bit-cell comprising a non-planar transistor and an FE capacitor with templating or texturing layer, in accordance with some embodiments.
FIG. 3 illustrates a 3D view of the FE capacitive structure with templating or texturing layer, in accordance with some embodiments.
FIG. 4 illustrates a 3D view of the FE capacitive structure where a bottom electrode and a templating layer are integrated together, in accordance with some embodiments.
FIG. 5 illustrates a 3D view of the FE capacitive structure where a bottom electrode, a templating layer, and a barrier layer are integrated together, in accordance with some embodiments.
FIG. 6 illustrates a flowchart of a method for forming the FE capacitive structure of FIG. 3, in accordance with some embodiments.
FIG. 7 illustrates a flowchart of a method for forming the FE capacitive structure of FIG. 4, in accordance with some embodiments.
FIG. 8 illustrates a flowchart of a method for forming the FE capacitive structure of FIG. 5, in accordance with some embodiments.
