The drain contact 208b is coupled to via 209b, which is coupled to metal layer 110. Metal layer 210 is the bit-line, which extends along the x-axis. The source contact 208a is coupled to via 209b. Any suitable material can be used for drain and source contacts 208a/n and via 209a/b. For example, one or more of Ti, N, Si, Ta, Cu, Al, Au, W, or Co can be used for drain and source contacts 208a/n and via 209a/b. Via 209b is coupled to FE capacitor Cfe 211 that comprises a stack of layers including a templating layer deposited below a ferroelectric layer to enable crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates. In some embodiments, the stack of layers that forms a ferroelectric device or capacitor Cfe 211 comprises a bottom barrier layer, a templating layer on the bottom barrier layer, a bottom electrode on the templating layer, a ferroelectric layer on the bottom electrode, a top electrode on the ferroelectric layer, and a top barrier on the top electrode. In some embodiments, each layer may be a single layer. In some embodiments, some or all layers comprise a superlattice of two or more different materials. In some embodiments, the templating layer is self-crystalized. In some embodiments, the templating layer has an in-plane lattice constant. In some embodiments, the in-plane lattice constant is within about 5% of a lattice constant of the bottom electrode and the ferroelectric layer. In some embodiments, the top and/or bottom electrodes includes one or more of: Sr, Ru, O, La, Mn, or Ti.