The driving voltage lines PLa, PLb, and PL and the electrode voltage lines HL may be connected to each pixel P through the contact hole CNT. Because the driving voltage lines PLa, PLb, and PL extend along the second direction, and the electrode voltage line HL electrically connected to the driving voltage lines PLa, PLb, and PL extend along the first direction intersecting or crossing the second direction, a plurality of driving voltage lines PLa, PLb, and PL and a plurality of electrode voltage lines HL may thus form a mesh structure. Accordingly, even when the driving voltage lines PLa and PLb around the transmission area TA are disconnected without bypassing (e.g., passing through) the transmission area TA, the driving voltage ELVDD may be substantially uniformly applied to a plurality of pixels P.
The electrode voltage line HL may extend from the second storage capacitor plate CE2 of the storage capacitor Cst as described with reference to
In some embodiments, the lines bypassing (e.g., passing through) the periphery of the transmission area TA may be integrated with the lines arranged in the display area DA. In other embodiments, the lines bypassing the periphery of the transmission area TA may be provided as connection lines arranged in the same layer as, or in different layers than, the lines arranged in the display area DA.