Semiconductor memory device and method for manufacturing the same
地域：
Minato-ku
摘要
A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
說明書
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This application is a continuation of and claims the benefit of priority under 35 U.S.C. § 120 from U.S. application Ser. No. 17/335,214 filed Jun. 1, 2021, which is a continuation of U.S. application Ser. No. 16/918,005 filed Jul. 1, 2020 (now U.S. Pat. No. 11,063,064 issued Jul. 13, 2021), which is a continuation of U.S. application Ser. No. 16/596,892 filed Oct. 9, 2019 (now U.S. Pat. No. 10,741,583 issued Aug. 11, 2020), which is a continuation of U.S. application Ser. No. 16/138,619 filed Sep. 21, 2018 (now U.S. Pat. No. 10,497,717 issued Dec. 3, 2019), which is a continuation of U.S. application Ser. No. 15/345,790 filed Nov. 8, 2016 (now U.S. Pat. No. 10,115,733 issued Oct. 30, 2018), which is a continuation of U.S. application Ser. No. 14/614,588 filed Feb. 5, 2015 (now U.S. Pat. No. 9,520,407 issued Dec. 13, 2016), and claims the benefit of priority under 35 U.S.C. § 119 from Japanese Patent Application No. 2014-021747 filed Feb. 6, 2014; the entire contents of each of which are incorporated herein by reference.
Embodiments described herein relate to a semiconductor memory device and a method for manufacturing the same.
權(quán)利要求
What is claimed is:1. A non-volatile memory device comprising: a substrate; an insulation film provided above the substrate; a first conductive layer provided above the insulation film; an upper interconnect structure including a first interconnection; electrodes provided between the first conductive layer and the upper interconnect structure, the electrodes being arranged in a first direction perpendicular to the first conductive layer to constitute a stacked body and functioning control gates for memory cells; at least one semiconductor body extending through the electrodes in the first direction and having a circular shape in a cross section orthogonal to the first direction, one end of the semiconductor body being electrically connected to the first conductive layer, and the other end of the semiconductor body being electrically connected to the first interconnection; and a conductive body extending through the electrodes in the first direction and in a second direction orthogonal to the first direction between the first conductive layer and the upper interconnect structure, the conductive body including a metal portion and being electrically connected to the first conductive layer, an outer diameter of the circular shape semiconductor body being smaller than a width of the metal portion of the conductive body at a same level in the first direction, the width being along a third direction orthogonal to the first direction and the second direction. 2. The device according to claim 1 ,wherein the metal portion contains tungsten. 3. The device according to claim 1 ,wherein the metal portion is positioned at a same level in the first direction as the stacked body of the electrodes. 4. The device according to claim 1 ,wherein each of the electrodes extends in the second direction. 5. The device according to claim 4 ,wherein the first interconnection extends in the third direction. 6. The device according to claim 1 ,wherein each of the electrodes is a polycrystalline silicon film or a metal film. 7. The device according to claim 1 ,wherein the first conductive layer functions a source layer. 8. The device according to claim 1 ,wherein the first conductive layer includes a polycrystalline silicon film. 9. The device according to claim 1 ,wherein the upper interconnect structure further includes a second interconnection and the conductive body electrically connects the first conductive layer and the second interconnection. 10. The device according to claim 1 ,wherein the conductive body divides the stacked body of the electrodes into plural portions in the third direction. 11. The device according to claim 1 , further comprising:a metal plug provided between the other end of the semiconductor body and the first interconnection. 12. A non-volatile memory device comprising:a substrate; an insulation film provided above the substrate; a first conductive layer provided above the insulation film; an upper interconnect structure including a first interconnection; electrodes provided between the first conductive layer and the upper interconnect structure, the electrodes being arranged in a first direction perpendicular to the first conductive layer to constitute a stacked body and functioning control gates for memory cells; at least one semiconductor body extending through the electrodes in the first direction, one end of the semiconductor body being electrically connected to the first conductive layer, and the other end of the semiconductor body being electrically connected to the first interconnection; and a conductive body electrically connected to the first conductive layer, the conductive body extending in the first direction between the first conductive layer and the upper interconnect structure and including a metal portion embedded in a slit extending in a second direction orthogonal to the first direction, the slit dividing the stacked body into plural portions in a third direction orthogonal to the first direction and the second direction. 13. The device according to claim 12 ,wherein the metal portion contains tungsten. 14. The device according to claim 12 ,wherein the metal portion is positioned at a same level in the first direction as the stacked body of the electrodes. 15. The device according to claim 12 ,wherein each of the electrodes extends in the second direction. 16. The device according to claim 15 ,wherein the first interconnection extends in the third direction. 17. The device according to claim 12 ,wherein each of the electrodes is a polycrystalline silicon film or a metal film. 18. The device according to claim 12 ,wherein the first conductive layer functions a source layer. 19. The device according to claim 12 ,wherein the first conductive layer includes a polycrystalline silicon film. 20. The device according to claim 12 ,wherein the semiconductor body has a circular shape in a cross section orthogonal to the first direction and an outer diameter of the circular shape semiconductor body is smaller than a width of the metal portion of the conductive body at a same level in the first direction, the width being along the third direction.
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