Semiconductor memory devices and methods of manufacturing thereof
地域：
Hsinchu
摘要
A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.
說明書
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This application claims priority to and the benefit of U.S. Provisional Application No. 63/156,755, filed Mar. 4, 2021, entitled “3D MEMORY DEVICES HAVING VARYING CHANNEL LAYER WIDTH,” which is incorporated herein by reference in its entirety for all purposes.
The present disclosure generally relates to semiconductor devices, and particularly to methods of making a 3-dimensional (3D) memory device.
The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
權利要求
What is claimed is:1. A semiconductor device, comprising:a first conductive structure extending along a vertical direction; a second conductive structure extending along the vertical direction, wherein the second conductive structure is spaced apart from the first conductive structure along a first lateral direction; a plurality of third conductive structures each extending along the first lateral direction, wherein the plurality of third conductive structures are disposed across the first and second conductive structures; and a first semiconductor channel extending along the vertical direction; wherein the first semiconductor channel is disposed between the plurality of third conductive structures and the first conductive structure, and between the plurality of third conductive structures and the second conductive structure; and wherein the first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. 2. The semiconductor device of claim 1 , wherein the first varying width increases with an increasing height of the first and second conductive structures, while the second varying width decreases with an increasing height of the first semiconductor channel. 3. The semiconductor device of claim 1 , wherein the first varying width having a first portion increases and a second portion decreases, with an increasing height of the first and second conductive structures, while the second varying width having a first portion decreases and a second portion increases with an increasing height of the first semiconductor channel. 4. The semiconductor device of claim 1 , wherein the first varying width having a first portion decreases and a second portion increases, with an increasing height of the first and second conductive structures, while the second varying width having a first portion increases and a second portion decreases with an increasing height of the first semiconductor channel. 5. The semiconductor device of claim 1 , wherein the first conductive structure and the second conductive structure are in contact with end portions of a sidewall of the first semiconductor channel, respectively. 6. The semiconductor device of claim 1 , further comprising a first memory film extending along the vertical direction and disposed between the first semiconductor channel and the plurality of third conductive structures. 7. The semiconductor device of claim 6 , wherein each of the plurality of third conductive structures, the first conductive structure, the second conductive structure, a portion of the first semiconductor channel, and a portion of the first memory film collectively operate as a first memory cell. 8. The semiconductor device of claim 7 , further comprising:a plurality of fourth conductive structures each extending along the first lateral direction, wherein the plurality of fourth conductive structures are disposed across the first and second conductive structures; a second semiconductor channel extending along the vertical direction, wherein the second semiconductor channel is disposed between the plurality of fourth conductive structures and the first conductive structure, and between the plurality of fourth conductive structures and the second conductive structure; and a second memory film extending along the vertical direction and disposed between the second semiconductor channel and the plurality of fourth conductive structures; wherein the second semiconductor channel has the second varying width along the second lateral direction. 9. The semiconductor device of claim 8 , wherein each of the plurality of fourth conductive structures, the first conductive structure, the second conductive structure, a portion of the second semiconductor channel, and a portion of the second memory film collectively operate as a second memory cell. 10. A memory device, comprising:a first bit/source line extending along a vertical direction; a second bit/source line extending along the vertical direction; a first word line extending along a first lateral direction; a first memory film extending along the vertical direction, the first memory film in contact with the first word line; and a first semiconductor channel extending along the vertical direction, the first semiconductor channel disposed between the first bit/source line and the first memory film; wherein the first and second bit/source lines each have a first width extending along the first lateral direction, the first width increasing with an increasing height of the bit/source line; and wherein the first semiconductor channel has a second width extending along a second lateral direction perpendicular to the first lateral direction, the second width decreasing with an increasing height of the first semiconductor channel. 11. The memory device of claim 10 , wherein the first bit/source line, the second bit/source line, the first word line, a portion of the first semiconductor channel, and a portion of the first memory film collectively operate as a first memory cell. 12. The memory device of claim 10 , further comprising:a second word line extending along the first lateral direction, the second word line disposed opposite the first bit/source line from the first word line along the second lateral direction; a second memory film extending along the vertical direction, the second memory film in contact with the second word line; and a second semiconductor channel extending along the vertical direction, the second semiconductor channel disposed between the first bit/source line and the second memory film, and between the second bit/source line and the second memory film; wherein the second semiconductor channel has the second width extending along the second lateral direction. 13. The memory device of claim 12 , wherein the first bit/source line, the second bit/source line, the second word line, a portion of the second semiconductor channel, and a portion of the second memory film collectively operate as a second memory cell. 14. The memory device of claim 10 , further comprising a third word line extending along the first lateral direction, the third word line is either below or above the first word line along the vertical direction. 15. The memory device of claim 14 , wherein the first bit/source line, the second bit/source line, the third word line, a portion of the first semiconductor channel, and a portion of the first memory film collectively operate as a third memory cell. 16. The memory device of claim 10 , wherein the first memory film includes a ferroelectric layer.
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