In some embodiments, a number of memory cells 102 can be defined in the semiconductor device 100. A memory cell 102 can be constituted by a BL, a SL, a portion of a semiconductor channel, a portion of a memory film, and a word line (WL) (which will be discussed below). In the configuration of example FIG. 1, within one of the rows of the array, a number of memory cells 102 can be formed on the opposite sides of each pair of the BL and SL. For example, a first memory cell 102 can be partially defined by a portion of a memory film 114 and a portion of a semiconductor channel 112 disposed on one side of each pair of SL 106 and BL 108, and a second memory cell 102 can be partially defined by a portion of a memory fill 114 and a portion of a semiconductor channel 112 disposed on the other side of that pair of SL 106 and BL 108. Alternatively stated, these two memory cells 102 may share one pair of BL and SL. Further, each row can extend along the vertical direction (e.g., the Z-direction) to include an additional number of memory cells, thereby forming a number of memory strings. It should be understood that the semiconductor device 100 shown in FIG. 1 is merely an illustrative example, and thus, the semiconductor device 100 can be formed in any of various other 3D configurations, while remaining within the scope of present disclosure.
