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Semiconductor memory devices and methods of manufacturing thereof

專利號
US11758734B2
公開日期
2023-09-12
申請人
Taiwan Semiconductor Manufacturing Company, Ltd.(TW Hsinchu)
發(fā)明人
Peng-Chun Liou; Zhiqiang Wu; Ya-Yun Cheng; Yi-Ching Liu; Meng-Han Lin
IPC分類
H10B51/20; H10B51/30
技術(shù)領(lǐng)域
channel,layers,in,trenches,direction,insulating,memory,layer,along,device
地域: Hsinchu

摘要

A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.

說明書

FIGS. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15A illustrate perspective views of an example semiconductor device (or a portion of the example semiconductor device) during various fabrication stages, made by the method of FIGS. 2A-B, in accordance with some embodiments.

FIGS. 15B, 15C, 15D illustrate a top view, a cross-sectional view cut along a first lateral cross-section (e.g., along the X-direction), and a cross-sectional view cut along a second lateral cross-section (e.g., along the Y-direction), respectively, of the example semiconductor device, in accordance with some embodiments.

FIGS. 16A-B are plots of semiconductor channel thickness versus channel length and a cell current versus channel length, respectively, of the example semiconductor device of FIGS. 15A-D, in accordance with some embodiments.

FIGS. 17A-B illustrate cross-sectional views cut along a first lateral cross-section (e.g., along the X-direction) and a second lateral cross-section (e.g., along the Y-direction), respectively, of an example semiconductor device, in accordance with some embodiments.

FIGS. 18A-B are plots of a semiconductor channel thickness versus channel length and a cell current versus channel length, respectively, of the example semiconductor device of FIGS. 17A-B, in accordance with some embodiments.

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