The buffer layer 203 may be positioned on the base layer 201. The buffer layer is a functional layer for protecting the thin film transistor (TFT) from impurities such as alkali ions, flowing out from the base layer 201 or layers under the buffer layer. The buffer layer may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof. The buffer layer 203 may include a multi buffer and/or an active buffer.

The gate insulating layer 205 may be disposed on the buffer layer 203. The gate insulating layer 205 may be formed of an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), or may be formed of an insulating organic material.

A panel identification layer (PIL) 204′ may be provided on the gate insulating layer 205. The panel identification layer (PIL) 204′ is disposed on the same layer as the gate electrode 204 of the display area AA, and may be formed of the same material as the gate electrode 204 of the display area AA. For example, the panel identification layer (PIL) 204′ may be formed of magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof or the like.

A lower protective layer 207′ may be disposed on the panel identification layer 204′. The lower protective layer 207′ is disposed on the same layer as the interlayer insulating layer 207 of the display area AA, and may be formed of the same material as the interlayer insulating layer 207 of the display area AA. For example, the lower protective layer 207′ may be formed of an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), or may be formed of an insulating organic material.