3D ferroelectric memory
地域：
Hsin-Chu
摘要
Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.
說明書
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This Application is a Divisional of U.S. application Ser. No. 16/903,545, filed on Jun. 17, 2020, which claims the benefit of U.S. Provisional Application No. 62/924,736, filed on Oct. 23, 2019. The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety.
Two-dimensional (2D) memory arrays are prevalent in electronic devices and may include, for example, NOR flash memory arrays, NAND flash memory arrays, dynamic random-access memory (DRAM) arrays, and so on. However, 2D memory arrays are reaching scaling limits and are hence reaching limits on memory density. Three-dimensional (3D) memory arrays are a promising candidate for increasing memory density and may include, for example, 3D NAND flash memory arrays, 3D NOR flash memory arrays, and so on.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
權利要求
What is claimed is:1. A method for forming a memory device, the method comprising:depositing a memory film over a substrate, wherein the memory film comprises a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers; performing a first etch into the memory film to form a trench through the memory film; recessing a sidewall of the source/drain dielectric layer relative to sidewalls of the source/drain layers through the trench to form a recess; depositing a semiconductor layer filling the recess and the trench; performing a second etch into the semiconductor layer to clear the semiconductor layer from the trench; depositing a ferroelectric layer lining the trench and further lining the semiconductor layer at the recess; and depositing an electrode layer filling the trench over the ferroelectric layer. 2. The method according to claim 1 , further comprising:performing a third etch into the electrode layer to form a plurality of control gate electrodes bordering the semiconductor layer at the recess. 3. The method according to claim 1 , further comprising:depositing a high k gate dielectric layer lining the trench between the performing of the second etch and the depositing of the ferroelectric layer. 4. The method according to claim 1 , wherein the semiconductor layer is deposited on the sidewall of the source/drain dielectric layer and the sidewalls of the source/drain layers, and wherein the semiconductor layer is cleared from the sidewalls of the source/drain layers but not the sidewall of the source/drain dielectric layer by the second etch. 5. The method according to claim 1 , further comprising:depositing a second memory film over the memory film, wherein the second memory film comprises a pair of second source/drain layers and a second source/drain dielectric layer between the second source/drain layers, wherein the first etch is also performed into the second memory film, and wherein the recessing recesses a sidewall of the second source/drain dielectric layer relative to sidewalls of the second source/drain layers through the trench to form a second recess simultaneous with the recess. 6. The method according to claim 1 , wherein the recessing recesses a second sidewall of the source/drain dielectric layer relative to second sidewalls of the source/drain layers through the trench to form a second recess, and wherein the second recess is on an opposite side of the trench as the recess. 7. A method for forming a memory device, the method comprising:depositing a memory film over a substrate, wherein the memory film comprises a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers; patterning the memory film to form a trench through the memory film, wherein the source/drain layers and the source/drain dielectric layer form a common sidewall in the trench; forming a semiconductor channel inset into the common sidewall, between the source/drain layers, and exposed from the trench; depositing a data storage layer and a gate dielectric layer lining the semiconductor channel in the trench, wherein the data storage layer is in an orthorhombic phase and is distinct from the gate dielectric layer; and depositing an electrode layer in the trench and separated from the semiconductor channel by the data storage layer and the gate dielectric layer. 8. The method according to claim 7 , wherein the forming of the semiconductor channel comprises:performing a wet etch into the source/drain dielectric layer, through the trench, to form a recess at the source/drain dielectric layer; depositing a semiconductor layer lining the trench and the recess; and performing a dry etch into the semiconductor layer to segment the semiconductor layer into a plurality of semiconductor channels, including the semiconductor channel. 9. The method according to claim 8 , wherein the pair of source/drain layers comprises a first source/drain layer and a second source/drain layer overlying the first source/drain layer, and wherein a portion of the semiconductor layer corresponding to the semiconductor channel underlies the second source/drain layer during the dry etch. 10. The method according to claim 7 , further comprising:performing a planarization into the electrode layer to a top surface of the data storage layer; and patterning the electrode layer to form a plurality of openings extending through a portion of the electrode layer in the trench, wherein the openings segment the portion of the electrode layer into a plurality of electrodes in the trench. 11. The method according to claim 7 , wherein the patterning of the memory film forms a second trench through the memory film, and wherein the data storage layer, the gate dielectric layer, and the electrode layer are further deposited in the second trench. 12. The method according to claim 11 , further comprising:patterning the electrode layer to form a plurality of first electrodes spaced from each other in the trench in a dimension, and to further form a plurality of second electrodes spaced from each other in the second trench in the dimension, and wherein the first and second electrodes alternate in the dimension. 13. The method according to claim 7 , wherein the source/drain layers and the source/drain dielectric layer form a second common sidewall in the trench and on an opposite side of the trench as the common sidewall, and wherein the method further comprises:forming a second semiconductor channel inset into the second common sidewall, between the source/drain layers, and exposed from the trench. 14. A method for forming a memory device, the method comprising:depositing a memory film over a substrate, wherein the memory film comprises a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers; performing a first etch into the memory film to form a trench through the memory film; performing a second etch into the source/drain dielectric layer through the trench to expand a width of the trench at the source/drain dielectric layer relative to a width of the trench at the source/drain layers; forming a pair of semiconductor channels in the trench, wherein the semiconductor channels border the source/drain dielectric layer respectively on opposite sides of the trench and are at the expanded width of the trench; depositing a ferroelectric layer lining the trench and further lining the semiconductor channels; and depositing an electrode layer between and bordering the semiconductor channels in the trench, wherein the ferroelectric layer separates the electrode layer from the semiconductor channels. 15. The method according to claim 14 , further comprising:depositing a cap dielectric layer overlying a via, wherein the memory film is deposited overlying the cap dielectric layer; depositing a spacer layer lining the trench over the ferroelectric layer; and etching back the ferroelectric layer and the spacer layer to extend the trench through the cap dielectric layer to the via, wherein the electrode layer is deposited after the etching back. 16. The method according to claim 15 , wherein the cap dielectric layer is deposited over a second via, which is electrically shorted to the via by a wire underlying the via and the second via, wherein the first etch forms a second trench through the memory film, wherein the ferroelectric layer and the spacer layer are deposited lining the second trench, and wherein the etching back extends the second trench to the second via. 17. The method according to claim 14 , further comprising:depositing a high k dielectric layer lining the trench, wherein the ferroelectric layer is deposited over the high k dielectric layer. 18. The method according to claim 14 , further comprising:depositing a second memory film over the memory film, wherein the second memory film comprises a pair of second source/drain layers and a second source/drain dielectric layer between the second source/drain layers; wherein the first etch is further into the second memory film, such that the trench extends through the second memory film, and wherein the second etch expands a width of the trench at the second source/drain dielectric layer relative to a width of the trench at the second source/drain layers. 19. The method according to claim 14 , wherein the forming of the pair of semiconductor channels comprises:depositing a semiconductor layer filling the trench; and performing a third etch into the semiconductor layer to segment the semiconductor layer into the pair of semiconductor channels, wherein a top source/drain layer of the pair of source/drain layers overlies portions of the semiconductor layer corresponding to the semiconductor channels during the third etch. 20. The method according to claim 14 , further comprising:performing a third etch into the electrode layer to form a plurality of openings extending through a portion of the electrode layer in the trench, wherein the openings segment the portion of the electrode layer into a plurality of electrodes in the trench; and filling the openings with a dielectric material.
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