3D ferroelectric memory
摘要
說(shuō)明書(shū)
In some embodiments, a thickness Tgdl of the gate dielectric layer 110 (e.g., in an X direction) is less than about 2.5 nanometers or some other suitable value. In some embodiments, the thickness Tgdl is about 1.5-2.5 nanometers, about 1.5-1.75 nanometers, about 1.75-2.5 nanometers, or some other suitable value. If the thickness Tgdl is too small (e.g., less than about 1 nanometer or some other suitable value), leakage current may be high and hence data retention may be low. If the thickness Tgdl is too large (e.g., greater than about 2.5 nanometers or some other suitable value), the program and erase voltages may be large and the memory window (e.g., a difference between the program and erase threshold voltages) may be small. The former leads to low power efficiency, whereas the latter leads to low reliability.
The ferroelectric layer 112 is in the orthorhombic phase and may, for example, be or comprise hafnium oxide (e.g., HfO2) doped with: 1) aluminum to less than about 20 atomic percent; 2) silicon to less than about 5 atomic percent; 3) zirconium to less than about 50 atomic percent; 4) lanthanum to less than about 50 atomic percent; 5) strontium to less than about 50 atomic percent; or 6) some other suitable element. Other atomic percentages are, however, amenable. Additionally, or alternatively, the ferroelectric layer 112 may, for example, be or comprise some other suitable ferroelectric material(s). In some embodiments, a dielectric constant of the ferroelectric layer 112 is greater than that of the gate dielectric layer 110.
