While FIGS. 3A-3G illustrate cross-sectional views 300A-300G of some alternative embodiments of FIG. 2A in which constituents are modified, it is to be appreciated that the modifications may also be applied to any of FIGS. 2B-2D. For example, when applying the modifications of FIG. 3A to FIGS. 2B-2D, the gate dielectric layer 110 and the ferroelectric layer 112 may be cleared from atop the array dielectric layer 210 of the second memory array 204b in FIGS. 2B and 2C. FIG. 2D may be remain unchanged. While FIG. 2D is described with regard to FIGS. 2A-2C, any of FIGS. 3A-3G may be taken along line C in embodiments of FIG. 2D which have been modified as necessary as described above. For example, FIG. 3G may be taken along line C in alternative embodiments of FIG. 2D in which the dielectric structure 116 has been replaced with the cavities 302. As another example, FIGS. 3A-3C may be taken along line C in the embodiments of FIG. 2D without modification of FIG. 2D.
