The 3D memory array 202 is uncovered by the gate dielectric layer 110 and the ferroelectric layer 112 as in FIG. 3A. As such, the gate dielectric layer 110 comprises a plurality of discrete gate dielectric segments, and the ferroelectric layer 112 comprises a plurality of discrete ferroelectric segments. A plurality of spacers 804 separate the control gate electrodes 114 from the ferroelectric segments. Further, the dielectric structure 116 extends through the cap dielectric layer 802, the gate dielectric segments, and the ferroelectric segments. The spacers 804 may be or comprise, for example, silicon nitride and/or some other suitable dielectric(s).

As seen hereafter, the spacers 804 may be formed by a self-aligned process and used with a top one of the array dielectric layers 210 as a mask to form openings within which the control gate electrodes 114 are formed. This may lead to a reduction in the number of photomasks used while forming the 3D memory array 202. Because photolithography is expensive, the reduction may lead to a substantial cost savings. Further, as seen hereafter, the spacers 804 protect the ferroelectric layer 112 while forming openings within which the control gate electrodes 114 are formed. This, in turn, reduces the likelihood of damage to the ferroelectric layer 112 and may hence enhance performance of the MFIS memory cells 102. Further yet, by forming the bottom electrode vias BEV independent of the control gate electrodes 114, aspect ratios (e.g., ratios of height to width) of the openings within which the control gate electrodes 114 are formed may be reduced. This, in turn, may reduce the complexity of the etch used to form the openings and may enlarge the process window (e.g., the resiliency).