As illustrated by the top and cross-sectional views 1500A, 1500B of FIGS. 15A and 15B, a gate dielectric layer 110, a ferroelectric layer 112, and a control electrode layer 1502 (collectively the trench layers) are formed filling the trenches 1102. The gate dielectric layer 110 is formed lining and partially filling the trenches 1102, and the ferroelectric layer 112 is formed lining and partially filling the trenches 1102 over the gate dielectric layer 110. The control electrode layer 1502 is formed filling a remainder of the trenches 1102 over the ferroelectric layer 112. In some embodiments, the control electrode layer 1502 is or comprises titanium nitride, doped polysilicon, tantalum nitride, tungsten, some other suitable conductive material(s), or any combination of the foregoing. In some embodiments, the ferroelectric layer 112 is or comprises doped hafnium oxide (e.g., doped with aluminum, silicon, zirconium, lanthanum, strontium, or the like) and/or some other suitable ferroelectric material(s). In some embodiments, the gate dielectric layer 110 is or comprises silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, lanthanum oxide, strontium titanium oxide, undoped hafnium oxide, or some other suitable dielectric material(s), or any combination of the foregoing. In some embodiments, the gate dielectric layer 110 is or comprises a high k dielectric layer.
