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3D ferroelectric memory

專利號
US11770935B2
公開日期
2023-09-26
申請人
Taiwan Semiconductor Manufacturing Company, Ltd.（TW Hsinchu）
發(fā)明人
Sheng-Chih Lai; Chung-Te Lin
IPC分類
H01L21/00; H10B51/20; H01L29/78; H01L21/28; H01L29/66; H10B51/30; H10B51/40
技術(shù)領(lǐng)域
mfis,dielectric,layer,drain,gate,memory,106u,106l,electrode,array
地域： Hsin-Chu

摘要

Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

說明書

The ferroelectric layer has a polarity representing a bit of data. During a program operation, a program voltage is applied across the ferroelectric layer from the control gate electrode to the semiconductor channel to set the polarity to a programmed state. During an erase operation, an erase voltage is applied across the ferroelectric layer from the control gate electrode to the semiconductor channel to set the polarity to an erased state. By employing the ferroelectric layer for data storage, as opposed to a silicon nitride layer, there is no dependence on carrier tunneling. As such, program and erase voltages may be reduced and program and erase speeds may be increased. For example, program and erase voltages may be reduced to less than about 5 volts and/or program and erase speeds may be reduced to less than about 100 nanoseconds. Other suitable values are, however, amenable. By reducing the program and erase voltages and by increasing the program and erase speeds, power consumption may be reduced.

With reference to FIGS. 1A-1C, various views 100A-100C of some embodiments of a MFIS memory cell 102 is provided. FIG. 1A corresponds to a cross-sectional view 100A along line A in FIG. 1C, whereas FIG. 1B corresponds to a cross-sectional view 100B along line B in FIG. 1C. Further, FIG. 1C corresponds to a top view 100C. The MFIS memory cell 102 may, for example, be or comprise a MFIS field-effect transistor (FET) or some other suitable type of semiconductor device having an MFIS stack.

權(quán)利要求

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