In the display panel, the first bridge line is connected to the first data line through a first via hole. The second bridge line is connected to the first scan line through a second via hole.

In the display panel, the insulating layers comprise:

a gate insulating layer disposed between the first metal layer and the second metal layer;

an interlayer insulating layer disposed between the second metal layer and the third metal layer; and

a planarization layer disposed between the third metal layer and the anode layer; and

wherein the first via hole penetrates the interlayer insulating layer, and the second via hole penetrates the gate insulating layer, the interlayer insulating layer, and the planarization layer.

In the display panel, in the ring-shaped wiring area, the first bridge line overlaps the second data line in a direction perpendicular to the display panel, and the second bridge line overlaps the second scan line in the direction perpendicular to the display panel.

In the display panel, in the ring-shaped wiring area, the second data line partially overlaps the second scan line, and orthographic projections of the second data line, the second scan line, the first bridge line, and the second bridge line on a substrate fall within a same arc line.

In the display panel, the second metal layer and the third metal layer are composed of a same material.

In the display panel, a difference between a block resistance of the data line and a block resistance of the first bridge line is less than or equal to 0.15Ω. A difference between a block resistance of the scan line and a block resistance of the second bridge line is less than or equal to 0.2Ω.