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Spin-orbit-torque magnetoresistive random-access memory

專利號(hào)
US11793001B2
公開日期
2023-10-17
申請人
International Business Machines Corporation(US NY Armonk)
發(fā)明人
Eric Raymond Evarts; Virat Vasav Mehta; Oscar van der Straten
IPC分類
H10B61/00; G11C11/16; H10N52/00; H10N52/01; H10N52/80
技術(shù)領(lǐng)域
sot,mram,layer,she,write,cell,stack,in,mtj,rail
地域: NY NY Armonk

摘要

A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure, forming a write line disposed in electrical contact with the SHE rail, forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack, and forming a read line disposed above and adjacent to the diode structure.

說明書

BACKGROUND

The disclosure relates generally to magnetoresistive random-access memory (MRAM). The disclosure relates particularly to spin-orbit torque MRAM structures controlled by a single transistor.

MRAM is a type of solid state, non-volatile memory that uses tunneling magnetoresistance (TMR) to store information. MRAM is made up of an electrically connected array of magnetoresistive memory elements, referred to as magnetic tunnel junctions (MTJs). Each MTJ includes a free layer and fixed layer that each include a layer of a magnetic material, and that are separated by a non-magnetic insulating tunnel barrier. The free layer has a variable magnetization direction, and the fixed layer has an invariable magnetization direction. An MTJ stores information by switching the magnetization state of the free layer. When the magnetization direction of the free layer is parallel to the magnetization direction of the fixed layer, the MTJ is in a low resistance state. Conversely, when the magnetization direction of the free layer is antiparallel to the magnetization direction of the fixed layer, the MTJ is in a high resistance state. The difference in resistance of the MTJ may be used to indicate a logical ‘1’ or ‘0’, thereby storing a bit of information. The TMR of an MTJ determines the difference in resistance between the high and low resistance states. A relatively high difference between the high and low resistance states facilitates read operations in the MRAM. MRAM cells can be formed as a vertical stack enabling device design options for increasing device memory cell element density while maintaining or even reducing the scale of devices.

權(quán)利要求

1
What is claimed is:1. An MRAM (magnetoresistive random-access memory) structure comprising:a spin-Hall-effect (SHE) rail;an spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure;a write line disposed in electrical contact with the SHE rail; anda read line disposed above and adjacent to the diode structure.2. The MRAM structure according to claim 1, wherein the SHE rail is disposed in electrical contact with a transistor.3. The MRAM structure according to claim 1, wherein diode structure comprises a metal-oxide-metal layered structure.4. The MRAM structure according to claim 1, wherein the free layer is disposed adjacent to the SHE rail.5. The MRAM structure according to claim 1, wherein the write line is disposed above the SHE rail.6. The MRAM structure according to claim 1, wherein the write line is disposed below the SHE rail.7. The MRAM structure according to claim 1, wherein the SHE rail comprises a material selected from the group consisting of Ta, Pt, W, Jr, and combinations thereof.8. The MRAM structure according to claim 1, wherein the diode structure comprises a TiO2/Ti layer stack.9. An MRAM (magnetoresistive random-access memory) structure comprising:a spin-Hall-effect (SHE) rail disposed in electrical contact with a transistor;an spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure;a write line disposed in electrical contact with the SHE rail; anda read line disposed above and adjacent to the diode structure.10. The MRAM structure according to claim 9, wherein diode structure comprises a metal-oxide-metal layered structure.11. The MRAM structure according to claim 9, wherein the free layer is disposed adjacent to the SHE rail.12. The MRAM structure according to claim 9, wherein the write line is disposed above the SHE rail.13. The MRAM structure according to claim 9, wherein the write line is disposed below the SHE rail.14. The MRAM structure according to claim 9, wherein the SHE rail comprises a material selected from the group consisting of Ta, Pt, W, Ir, and combinations thereof.15. The MRAM structure according to claim 9, wherein the diode structure comprises a TiO2/Ti layer stack.16. A method of fabricating a semiconductor device, the method comprising:forming a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor;forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure;forming a write line disposed in electrical contact with the SHE rail;forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack; andforming a read line disposed above and adjacent to the diode structure.17. The method of fabricating a semiconductor structure according to claim 16, wherein diode structure comprises a metal-oxide-metal layered structure.18. The method of fabricating a semiconductor structure according to claim 16, wherein the free layer is disposed adjacent to the SHE rail.19. The method of fabricating a semiconductor structure according to claim 16, wherein the write line is disposed above the SHE rail.20. The method of fabricating a semiconductor structure according to claim 16, wherein the write line is disposed below the SHE rail.
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