In an embodiment, the lower SOT MRAM cell stacks are formed using a patterning and etching process such as RIE. As shown in FIG. 5, layers 310-350 have been selectively etched away using ion-beam etching, leaving the SOT MRAM cell stack in contact with bottom electrode 120 and in electrical contact with a contact 110 of a device element (e.g., a transistor) of the underlying semiconductor device, a free layer 310, a tunnel barrier layer 320, a reference layer 330, diode stack 340, and hard mask 350. As shown in the figure, dielectric spacer material 510 and interlayer dielectric material 520 have been deposited upon the lower SOT MRAM cell stack.

In an embodiment, dielectric space material 510, such as SiN, is deposited upon the intermediate structure of the device, including the SOT-MRAM cell stacks. After deposition of the material 510, anisotropic etching, or other methods are used to remove the material from the horizontal surfaces of the device, leaving protective sidewalls of the material upon the vertical surfaces of the SOT-MRAM cell stacks. Subsequent to the formation of the protective sidewalls, an ILD material 520 is deposited upon the device and CMP processes are used to recess the ILD material 520, and hard mask 410, to the upper surface of the upper metal layer 348, of diode stack 340. The CP processes yield a polished upper device surface in preparation for the next step.