FIG. 4 is a schematic illustration of a simplified block diagram of an encoder in accordance with an embodiment.
FIG. 5 is a schematic illustration of options for signaling ARC parameters in accordance with prior art or an embodiment, as indicated.
FIG. 6 is an example of a syntax table in accordance with an embodiment.
FIG. 7 is a schematic illustration of a computer system in accordance with an embodiment.
FIG. 8 is an example of prediction structure for scalability with adaptive resolution change.
FIG. 9 is an example of a syntax table in accordance with an embodiment.
FIG. 10 is a schematic illustration of a simplified block diagram of parsing and decoding poc cycle per access unit and access unit count value.
FIG. 11 is a schematic illustration of a video bitstream structure comprising multi-layered sub-pictures.
FIG. 12 is a schematic illustration of a display of the selected sub-picture with an enhanced resolution.
FIG. 13 is a block diagram of the decoding and display process for a video bitstream comprising multi-layered sub-pictures.
FIG. 14 is a schematic illustration of 360 video display with an enhancement layer of a sub-picture.
