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Smart personal area network management

專利號(hào)
US11800499B1
公開日期
2023-10-24
申請(qǐng)人
Amazon Technologies, Inc.(US WA Seattle)
發(fā)明人
Sunil Felix Assao; Chiu Ngok Eric Wong
IPC分類
H04W48/16; H04W72/0446
技術(shù)領(lǐng)域
or,pan,schedule,210b,210a,beacon,gateway,timeslots,nodes,devices
地域: WA WA Seattle

摘要

Two or more personal area networks (or PANs) operating channel hopping schedules may be operated within a vicinity of one another with channel hopping schedules according to IEEE 802.15.4 that are separated by a frequency offset, and collisions between data transmitted by the respective devices of the networks may be avoided. Nodes of a first PAN transmit beacons identifying information regarding a first communications schedule. A node of a second PAN receives the beacon and establishes a second channel hopping schedule at the offset from the first communications schedule. Nodes of PANs may be programmed with communication modes that vary uplink or downlink slots based on quality-of-service or traffic requirements.

說(shuō)明書

In some embodiments, the processors of the devices 210A-1, 210A-2 . . . 210A-n or the devices 210B-1, 210B-2 . . . 210B-m may be configured to determine that a handshake has been accepted or refused by one or more gateways, and to execute one or more actions in response to the acceptance or refusal, e.g., to transfer data according to one or more protocols or standards, such as Transmission Control Protocol (or “TCP”), Transport Layer Security (or “TLS”), Secure Sockets Layer (“or “SSL”), or the others.

The processors of the devices 210A-1, 210A-2 . . . 210A-n or the devices 210B-1, 210B-2 . . . 210B-m may include a uniprocessor system including one processor, or a multiprocessor system including several processors (e.g., two, four, eight, or another suitable number), and may be capable of executing instructions. For example, in some embodiments, such processors may be a general-purpose or embedded processor implementing any of a number of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, or MIPS ISAs, or any other suitable ISA. Where the processors are components of a multiprocessor system, each of the processors within the multiprocessor system may operate the same ISA, or different ISAs.

權(quán)利要求

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