Semiconductor structure and manufacturing method thereof
地域：
Hefei
摘要
The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The method of manufacturing the semiconductor structure includes: providing a substrate; forming, on the substrate, a first initial conductive layer, a sacrificial layer and a first mask layer with a pattern that are stacked sequentially, a thickness of the sacrificial layer being 10 nm-20 nm; and etching, with the first mask layer as a mask, the first initial conductive layer and the substrate to form a bit line (BL) contact region.
說(shuō)明書
This is a continuation of International Application No. PCT/CN2022/076312, filed on Feb. 15, 2022, which claims the priority to Chinese Patent Application 202110811874.5, titled “SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF”, filed with China National Intellectual Property Administration (CNIPA) on Jul. 19, 2021. The entire contents of International Application No. PCT/CN2022/076312 and Chinese Patent Application 202110811874.5 are incorporated herein by reference.
The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor structure and a manufacturing method thereof.
The dynamic random access memory (DRAM) is a semiconductor memory that randomly writes and reads data at high speeds, and is widely used in data storage devices.
A DRAM usually includes a plurality of repeated memory cells, each of which includes a transistor and a capacitor. The transistor includes a gate electrically connected to a word line (WL), a source electrically connected to a bit line (BL) through a BL contact, and a drain electrically connected to the capacitor through a memory node contact. The voltage on the WL can control the on or off of the transistor, so as to read data information in the capacitor or write data information into the capacitor through the BL.
However, during formation of BL contacts, it is likely to form gaps in the BL contacts, which increases resistances of the BL contacts and reduces the transmission performance of the semiconductor structure.
權(quán)利要求
The invention claimed is:1. A method of manufacturing a semiconductor structure, comprising:providing a substrate; forming, on the substrate, a first initial conductive layer and a sacrificial layer that are stacked sequentially, a thickness of the sacrificial layer being 10 nm-20 nm; forming a first mask layer with a pattern on the sacrificial layer; removing, with the first mask layer as a mask, the sacrificial layer, a part of the first initial conductive layer and a part of the substrate to form a bit line contact region in the first initial conductive layer and the substrate, wherein a retained first initial conductive layer forms a first conductive layer, and a thickness of the first conductive layer is ?-? of a thickness of the first initial conductive layer; and forming a second conductive layer in the bit line contact region, the second conductive layer filling the bit line contact region. 2. The method of manufacturing the semiconductor structure according to claim 1 ,wherein a depth of the bit line contact region is 34 nm-42 nm. 3. The method of manufacturing the semiconductor structure according to claim 2 , wherein the forming a first mask layer with a pattern on the sacrificial layer comprises:forming a first photoresist layer on the first mask layer; patterning the first photoresist layer to form a first mask pattern in the first photoresist layer, wherein the first mask pattern comprises a plurality of first opening regions arranged at intervals and a first shielding region for separating each of the first opening regions; and removing the first mask layer exposed in the first opening region, to form a pattern in the first mask layer. 4. The method of manufacturing the semiconductor structure according to claim 3 , wherein the forming a second conductive layer in the bit line contact region comprises:forming a second initial conductive layer in the bit line contact region, the second initial conductive layer extending out of the bit line contact region, and covering the first conductive layer; and removing the second initial conductive layer by a certain thickness, such that a retained second initial conductive layer forms the second conductive layer, and the second conductive layer and the first conductive layer are connected into a whole to form a bit line contact layer. 5. The method of manufacturing the semiconductor structure according to claim 4 , wherein the second initial conductive layer is removed by the certain thickness with chemical mechanical polishing. 6. The method of manufacturing the semiconductor structure according to claim 1 , wherein the first mask layer comprises a first hard mask layer and a first silicon oxynitride layer that are stacked sequentially, and the first hard mask layer is provided on the sacrificial layer. 7. The method of manufacturing the semiconductor structure according to claim 6 , after the providing a substrate, and before the forming, on the substrate, a first initial conductive layer and a sacrificial layer that are stacked sequentially, further comprising:forming a first insulating layer on the substrate. 8. The method of manufacturing the semiconductor structure according to claim 7 , wherein the first conductive layer and the second conductive layer are made of a same material comprising polycrystalline silicon. 9. The method of manufacturing the semiconductor structure according to claim 8 , wherein the sacrificial layer is made of a material comprising silicon oxide; and the first insulating layer is made of a material comprising silicon nitride. 10. The method of manufacturing the semiconductor structure according to claim 4 , after the removing the second initial conductive layer by a certain thickness, such that a retained second initial conductive layer forms the second conductive layer, and the second conductive layer and the first conductive layer are connected into a whole to form a bit line contact layer, further comprising:forming, on the bit line contact layer, a bit line conductive layer and a second mask layer with a pattern that are stacked sequentially; and removing, with the second mask layer with the pattern as a mask, a part of the bit line conductive layer and a part of the bit line contact layer, such that a retained bit line conductive layer forms a bit line, and a retained bit line contact layer forms a bit line contact. 11. The method of manufacturing the semiconductor structure according to claim 10 , wherein the forming, on the bit line contact layer, a bit line conductive layer and a second mask layer with a pattern that are stacked sequentially comprises:forming a second photoresist layer on the second mask layer; patterning the second photoresist layer to form a second mask pattern in the second photoresist layer, wherein the second mask pattern comprises a plurality of second opening regions arranged at intervals and a second shielding region for separating each of the second opening regions; and removing the second mask layer exposed in the second opening region, to form a pattern in the second mask layer. 12. The method of manufacturing the semiconductor structure according to claim 11 , wherein the second mask layer comprises an amorphous carbon layer, a second silicon oxynitride layer, a second hard mask layer and a third silicon oxynitride layer that are stacked sequentially, and the amorphous carbon layer is provided on the bit line conductive layer. 13. The method of manufacturing the semiconductor structure according to claim 12 , wherein the bit line conductive layer comprises a first bit line conductive layer and a second bit line conductive layer that are stacked sequentially, and the first bit line conductive layer is provided on the bit line contact layer. 14. The method of manufacturing the semiconductor structure according to claim 13 , wherein the forming, on the bit line contact layer, a bit line conductive layer and a second mask layer with a pattern that are stacked sequentially further comprises:forming a second insulating layer on the bit line conductive layer.
意見反饋
使用該功能遇到問題
該功能需要專業(yè)版企業(yè)版VIP權(quán)限，您可以：
您也可以聯(lián)系官方QQ: 2157717237 電話: 13264338900