Semiconductor device and method of manufacturing semiconductor device
地域：
Kyoto
摘要
A semiconductor device includes: a semiconductor layer having a main surface; a first conductive type well region formed on a surface portion of the main surface of the semiconductor layer; a second conductive type source region formed on a surface portion of the well region; a second conductive type drain region formed on the surface portion of the well region at an interval from the source region; a planar gate structure formed on the main surface of the semiconductor layer so as to face a first conductive type channel region disposed between the source region and the drain region; and a memory structure disposed adjacent to a lateral side of the planar gate structure, and including an insulating film formed on the channel region and a charge storage film facing the channel region with the insulating film interposed between the charge storage film and the channel region.
說明書
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This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-091400, filed on May 26, 2020, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device.
A semiconductor device provided with a non-volatile memory is known. In a memory cell provided in such a semiconductor device, a gate electrode is formed on a p-well region via a gate insulating film. On a lateral side of the gate electrode, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated on a resistance change portion formed on a surface portion of the p-well region. In this memory cell, writing is performed by injecting hot electrons generated in a vicinity of a drain region into the silicon nitride film. Since this memory cell is used as an OTPROM (One Time Programmable Read Only Memory), no erase operation is performed except for a non-defective product confirmation test.
Some embodiments of the present disclosure provide a semiconductor device capable of repeatedly writing and erasing data with respect to a memory structure in a configuration in which the memory structure is arranged adjacent to a lateral side of a planar gate structure, and a method of manufacturing such a semiconductor device.
權利要求
What is claimed is:1. A semiconductor device, comprising:a semiconductor layer having a main surface; a first conductive type well region formed on a surface portion of the main surface of the semiconductor layer; a second conductive type source region formed on a surface portion of the well region; a second conductive type drain region formed on the surface portion of the well region at an interval from the source region; a planar gate structure that is formed on the main surface of the semiconductor layer so as to face a first conductive type channel region disposed between the source region and the drain region, and includes a gate insulating film formed on the main surface of the semiconductor layer and a gate electrode formed on the gate insulating film; a memory structure disposed adjacent to a lateral side of the planar gate structure, and including an insulating film formed on the channel region and a charge storage film facing the channel region with the insulating film interposed between the charge storage film and the channel region; a covering insulating film that covers the planar gate structure and the memory structure; and an interlayer insulating film that covers the covering insulating film, wherein the covering insulating film is in contact with the source region and the drain region, wherein the covering insulating film is in contact with the gate electrode, and wherein the interlayer insulating film is in contact with the covering insulating film in both a direction in which the gate insulating film, the gate electrode, and the covering insulating film are stacked, and a direction in which the memory structure is disposed adjacent to the lateral side of the planar gate structure. 2. The semiconductor device of claim 1 , wherein the memory structure is configured to inject hot electrons into the charge storage film during a write operation and to draw hot holes into the charge storage film during an erase operation. 3. The semiconductor device of claim 1 , wherein a thickness of the insulating film of the memory structure is smaller than a thickness of the gate insulating film. 4. The semiconductor device of claim 1 , wherein a recess for causing the main surface of the semiconductor layer to be recessed is provided on a lateral side of the gate insulating film, andwherein the insulating film of the memory structure is formed on the main surface of the semiconductor layer in the recess so as to be adjacent to the gate insulating film. 5. The semiconductor device of claim 1 , wherein the memory structure is located between the source region and the planar gate structure. 6. The semiconductor device of claim 1 , wherein the memory structure is located between the drain region and the planar gate structure. 7. The semiconductor device of claim 1 , wherein the charge storage film is an insulator different from the insulating film of the memory structure. 8. The semiconductor device of claim 7 , wherein the charge storage film is formed of SiN, and the insulating film of the memory structure is formed of SiO2. 9. The semiconductor device of claim 1 , wherein the charge storage film includes a first facing portion facing the channel region and a second facing portion facing the source region and the drain region. 10. The semiconductor device of claim 9 , wherein the first facing portion is larger than the second facing portion in a plan view. 11. The semiconductor device of claim 1 , wherein the insulating film of the memory structure includes a first insulating portion located between the semiconductor layer and the charge storage film, and a second insulating portion located between the planar gate structure and the charge storage film. 12. The semiconductor device of claim 1 , wherein the charge storage film includes a first storage portion that faces the main surface of the semiconductor layer with the insulating film of the memory structure interposed between the first storage portion and the main surface of the semiconductor layer, and a second storage portion that faces the planar gate structure with the insulating film of the memory structure interposed between the second storage portion and the planar gate structure. 13. The semiconductor device of claim 12 , wherein the charge storage film has a recess on a side opposite to the insulating film of the memory structure with respect to the first storage portion and on a side opposite to the insulating film of the memory structure with respect to the second storage portion, andwherein the memory structure further includes an insulating spacer disposed adjacent to the charge storage film in the recess. 14. The semiconductor device of claim 1 , wherein the covering insulating film covers the source region and the drain region on a lateral side of the memory structure, andwherein the semiconductor device further comprises: silicide films formed on surface portions of the source region and the drain region, respectively, on a side opposite to the memory structure with respect to the covering insulating film. 15. A method of manufacturing a semiconductor device, comprising:preparing a semiconductor wafer having a first conductive type well region formed on a surface portion of a main surface of the semiconductor wafer; forming a planar gate structure on the main surface of the semiconductor wafer, by forming a gate insulating film on the main surface of the semiconductor wafer and forming a gate electrode on the gate insulating film; forming a memory structure, which includes an insulating film disposed on the main surface and a charge storage film disposed on the insulating film, on a lateral side of the planar gate structure; forming a second conductive type source region on a surface portion of the well region on one side of the memory structure; forming a second conductive type drain region on the surface portion of the well region on another side of the memory structure, such that a first conductive type channel region facing the planar gate structure and the charge storage film is formed between the second conductive type drain region and the second conductive type source region; forming a covering insulating film to cover the planar gate structure and the memory structure; and forming an interlayer insulating film to cover the covering insulating film, wherein the covering insulating film is in contact with the source region and the drain region, wherein the covering insulating film is in contact with the gate electrode, and wherein the interlayer insulating film is in contact with the covering insulating film in both a direction in which the gate insulating film, the gate electrode, and the covering insulating film are stacked, and a direction in which the memory structure is disposed to be on the lateral side of the planar gate structure. 16. The method of claim 15 ,wherein forming the gate insulating film includes:forming a first base film on a surface portion of the main surface of the semiconductor wafer; and while forming the gate insulating film, forming a recess for causing the main surface to be recessed toward a lateral side of the gate insulating film by partially removing the first base film, and wherein forming the memory structure includes forming a second base film, which serves as a base of the insulating film of the memory structure, on a surface portion of the main surface of the semiconductor wafer in the recess. 17. The method of claim 16 , wherein the first base film and the second base film are formed by a thermal oxidation treatment method.
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