Referring to FIG. 4, the insulating film 41 may have a thickness T2 of 5 nm or more and 10 nm or less. The thickness T2 of the insulating film 41 may be, for example, 8 nm. The insulating film 41 is desirably thinner than the gate insulating film 31 (T2<T1).

The insulating film 41 includes a first surface 41a in contact with the first main surface 3 of the semiconductor layer 2, a second surface 41b on a side opposite to the semiconductor layer 2 with respect to the first surface 41a, a third surface 41c in contact with the side wall of the planar gate structure 30 (the side wall of the gate electrode 32), and a fourth surface 41d opposite to the planar gate structure 30 with respect to the third surface 41c.

The insulating film 41 includes a first insulating portion 46 extending along the first main surface 3 of the semiconductor layer 2 in the device region 6, and a second insulating portion 47 connected to the first insulating portion 46 and extending along the side wall of the planar gate structure 30. The insulating film 41 may be formed in an L-shape in cross section by connecting the first insulating portion 46 and the second insulating portion 47 at a right angle.

Since the insulating film 41 is not formed on the insulating buried object 12, the first insulating portion 46 is not provided in the connecting portion 40C of the memory structure 40 (see FIG. 3).