Referring subsequently to FIG. 7P, the covering insulating film 51 is formed on the device region 6 and the insulating buried object 12. The covering insulating film 51 is formed of silicon oxide in the present embodiment. The covering insulating film 51 may be formed by a CVD method.

Referring subsequently to FIG. 7Q, a resist mask 89 having a predetermined pattern is formed on the covering insulating film 51. The resist mask 89 exposes unnecessary portions of the covering insulating film 51 and covers other regions. Subsequently, the unnecessary portions of the covering insulating film 51 are removed by an etching method via the resist mask 89.

Specifically, as shown in FIG. 7R, a portion that covers the planar gate structure 30 and the memory structure 40 and a portion that covers the device region 6 on the lateral side of the memory structure 40 remain in the covering insulating film 51. In the covering insulating film 51, the portion covering the gate electrode 32 outside the device region 6 is removed to form the through-hole 52A. The etching method may be a dry etching method (e.g., an RIE method) and/or a wet etching method. Thereafter, the resist mask 89 is removed.