Memory array and methods of forming same
地域：
Hsinchu
摘要
A device includes a semiconductor substrate; a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor; and a second word line over the first word line. The second word line is insulated from the first word line by a first dielectric material, and the second word line providing a second gate electrode for a second transistor over the first transistor. The device further including a source line intersecting the first word line and the second word line; a bit line intersecting the first word line and the second word line; a memory film between the first word line and the source line; and a first semiconductor material between the memory film and the source line.
說(shuō)明書(shū)
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This application is a divisional of U.S. application Ser. No. 17/186,852, filed on Feb. 26, 2021, which claims the benefit of U.S. Provisional Application No. 63/148,639, filed on Feb. 12, 2021, which applications are hereby incorporated herein by reference.
Semiconductor memories are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. Semiconductor memories include two major categories. One is volatile memories; the other is non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered.
On the other hand, non-volatile memories can keep data stored on them. One type of non-volatile semiconductor memory is Ferroelectric random access memory (FeRAM, or FRAM). Advantages of FeRAM include its fast write/read speed and small size.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
權(quán)利要求
What is claimed is:1. A method, comprising:forming a first conductive line and a second conductive line over a semiconductor substrate, wherein the second conductive line is disposed over the first conductive line and is insulated from the first conductive line, and wherein the second conductive line is shorter than the first conductive line; patterning a first trench extending through the first conductive line and the second conductive line; depositing a memory film along sidewalls and a bottom surface of the first trench; depositing an oxide semiconductor (OS) layer over the memory film, the OS layer extending along the sidewalls and the bottom surface of the first trench; forming a first dielectric material over and contacting the OS layer; patterning a second trench and a third trench each extending through the first dielectric material; and after patterning the second trench and the third trench, forming a third conductive line in the second trench and a fourth conductive line in the third trench by filling the second trench and the third trench with a conductive material, wherein the first dielectric material extends continuously from the third conductive line to the fourth conductive line. 2. The method of claim 1 , further comprising:patterning a fourth trench through the first dielectric material before patterning the second trench and the third trench; and filling the fourth trench with a second dielectric material, wherein patterning the second trench and the third trench comprises an etching process that selectively etches the first dielectric material selective to the second dielectric material. 3. The method of claim 1 , further comprising forming a word line over and electrically connected to the first conductive line. 4. The method of claim 1 , wherein the first conductive line is electrically connected to a word line under the first conductive line. 5. The method of claim 1 , further comprising:forming a source line over and electrically connected to the third conductive line; and forming a bit line over and electrically connected to the fourth conductive line. 6. The method of claim 1 , wherein the third conductive line is electrically connected to a source line under the first conductive line, and wherein the fourth conductive line is electrically connected to a bit line under the first conductive line. 7. The method of claim 1 , wherein forming the first conductive line and the second conductive line over the semiconductor substrate comprises forming the first conductive line and the second conductive line over active devices on the semiconductor substrate. 8. The method of claim 1 , wherein forming the first dielectric material over and contacting the OS layer comprises:depositing a first portion of the first dielectric material in the first trench and on sidewalls of the OS layer; extending the first trench through the OS layer using the first portion of the first dielectric material as a mask; and depositing a second portion of the first dielectric material on the first portion of the first dielectric material. 9. A method, comprising:forming a first conductive line over a second conductive line, the first conductive line being separated from the second conductive line by a dielectric layer; etching a first opening, the first opening extending through the first conductive line, the second conductive line, and the dielectric layer; depositing an oxide semiconductor on opposing sidewalls of the first opening; after depositing the oxide semiconductor, filling remaining portions of the first opening with a first dielectric material, the first dielectric material extending between opposing sidewalls of the oxide semiconductor; and forming a third conductive line and a fourth conductive line extending through the first dielectric material, wherein the oxide semiconductor extends directly under the third conductive line. 10. The method of claim 9 , further comprising depositing a memory film along the opposing sidewalls of the first opening, wherein the oxide semiconductor is deposited over the memory film. 11. The method of claim 10 , wherein the memory film is a ferroelectric material. 12. The method of claim 10 , further comprising:etching a second opening, the second opening extending through the first conductive line, the second conductive line, and the dielectric layer; and filling the second opening with a second dielectric material, the second dielectric material extending between opposing sidewalls of the memory film. 13. The method of claim 9 , wherein forming the first conductive line comprises patterning the first conductive line so that the second conductive line extends laterally past the first conductive line. 14. The method of claim 9 , wherein the third conductive line is electrically connected to a bit line under the second conductive line, and wherein the fourth conductive line is electrically connected to a source line under the second conductive line, the bit line and the source line being disposed at a same level. 15. The method of claim 9 , wherein the third conductive line is electrically connected to a bit line above the first conductive line, and wherein the fourth conductive line is electrically connected to a source line above the first conductive line, the bit line and the source line being disposed at a same level. 16. A method, comprising:forming a first word line and a second word line over an active device on a semiconductor substrate, wherein the second word line is disposed over the first word line and is insulated from the first word line; patterning a first trench extending through the first word line and the second word line; depositing a memory film along sidewalls and a bottom surface of the first trench; depositing a semiconductor layer over the memory film and in the first trench; forming a first dielectric material over the semiconductor layer and in the first trench, wherein forming the first dielectric material comprises:depositing a first portion of the first dielectric material over the semiconductor layer in the first trench; etching an opening through the semiconductor layer using the first portion of the first dielectric material as a mask; and depositing a second portion of the first dielectric material in the first trench over the first portion of the first dielectric material and in the opening through the semiconductor layer; patterning a second trench and a third trench each extending through the first dielectric material; and forming a source line in the second trench and a bit line in the third trench, the source line being insulated from the bit line by remaining portions of the first dielectric material. 17. The method of claim 16 , further comprising patterning the second word line to be shorter than the first word line. 18. The method of claim 16 , wherein the semiconductor layer comprises indium. 19. The method of claim 18 , wherein the semiconductor layer comprises InxGayZnzMO, wherein M is Ti, Al, Ag, Si, or Sn, and wherein X, Y, and Z are each a number between 0 and 1. 20. The method of claim 16 , further comprising:patterning a fourth trench through the first dielectric material before patterning the second trench and the third trench; and filling the fourth trench with a second dielectric material, wherein patterning the second trench and the third trench comprises an etching process that selectively etches the first dielectric material at a rate faster than that of the second dielectric material.
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