The multi-layer stack 58 includes alternating layers of conductive layers 54A-D (collectively referred to as conductive layers 54) and dielectric layers 52A-C (collectively referred to as dielectric layers 52). The conductive layers 54 may be patterned in subsequent steps to define the conductive lines 72 (e.g., word lines). The conductive layers 54 may comprise a conductive material, such as, copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and the dielectric layers 52 may comprise an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The conductive layers 54 and dielectric layers 52 may be each formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), or the like. Although FIGS. 3A and 3B illustrate a particular number of conductive layers 54 and dielectric layers 52, other embodiments may include a different number of conductive layers 54 and/or dielectric layers 52.

FIGS. 4-11, 12A and 12B are views of intermediate stages in the manufacturing a staircase structure of the memory array 200, in accordance with some embodiments. FIGS. 4 through 11 and 12B are illustrated along reference cross-section B-B′ illustrated in FIG. 1. FIG. 12A is illustrated in a three-dimensional view.