As further illustrated in FIG. 12B, a removal process is then applied to the IMD 70 to remove excess dielectric material over the multi-layer stack 58. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the multi-layer stack 58 such that top surfaces of the multi-layer stack 58 and IMD 70 are level after the planarization process is complete.

FIGS. 13-16, 17A and 17B are views of intermediate stages in the manufacturing of the memory array 200, in accordance with some embodiments. In FIGS. 13-16, 17A and 17B, trenches are patterned in the multi-layer stack 58, thereby defining the conductive lines 72. The conductive lines 72 may correspond to word lines in the memory array 200, and the conductive lines 72 may further provide gate electrodes for the resulting TFTs of the memory array 200. FIG. 17A is illustrated in a three-dimensional view. FIGS. 13 through 16 and 17B are illustrated along reference cross-section C-C′ illustrated in FIG. 1A.

In FIG. 13, a hard mask 80 and a photoresist 82 are deposited over the multi-layer stack 58. The hard mask layer 80 may include, for example, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The photoresist 82 can be formed by using a spin-on technique, for example.