The lateral surface of the main terminal 70 is a surface that has a smaller area than that of the plate surface. The main terminals 70C and the 70E are arranged next to each other. In a configuration in which the main terminals 70 includes the multiple main terminals 70C and the multiple main terminals 70E, when the main terminals 70C and the main terminals 70E are arranged next to each other, the main terminals 70C and the main terminal 70E are located alternately. The main terminals 70C and the main terminals 70E are arranged in order.
As shown in FIG. 7, three or more main terminals 70 that are arranged continuously next to each other in the X direction are included in a main terminal group 71. As described above, the main terminals 70C and the main terminals 70E are arranged adjacent to each other. Thus, the main terminal group 71 includes both of the main terminal 70C and the main terminal 70E, as well as includes plural number of at least one of the main terminals 70C and the main terminal 70E. The main terminals 70 included in the main terminal group 71 are arranged such that at least a part of each main terminal 70 is located in a predetermined area A1. The area A1 is defined between an extension line EL1 virtually extending from an end surface 44 of the semiconductor chip 40 and an extension line EL2 virtually extending from an end surface 45 of the semiconductor chip 40 opposite to the end surface 44. The distance between the extension line EL1 and the extension line EL2 in the X direction corresponds to the width of the semiconductor chip 40 in the X direction, that is, an element width.
