The first pre-driver 120_1 operates according to the first control signal S_CTRL1. The second pre-driver 120_2 operates according to the second control signal S_CTRL2. Specifically, the first pre-driver 120_1 drives the first high-side transistor MH1 and the first low-side transistor ML1 according to the first control signal S_CTRL1. The second pre-driver 120_2 drives the second high-side transistor MH2 and the second low-side transistor ML2 according to the second control signal S_CTRL2. The first control signal S_CTRL1 includes at least a pulse signal for defining the duty ratio (or on time) of the first high-side transistor MH1. The second control signal S_CTRL2 includes at least a pulse signal for defining the duty ratio (or on time) of the second high-side transistor MH2.

In the first mode, the sequencer 140 starts up the first circuit block BLK1 and the second circuit block BLK2 at different timings with a system startup instruction or the turning-on of the power supply as a trigger. Also, with an application that supports a sleep mode, standby mode, or the like, such an arrangement may be capable of disabling only one from among the output of the first circuit block BLK1 and the output of the second circuit block BLK2 according to an instruction received from a host processor. Also, upon receiving a system stop instruction, the first circuit block BLK1 and the second circuit block BLK2 are stopped at different timings. The startup timing and the stop timing for each of the two blocks BLK1 and BLK2 may be settable by means of a register.