The buffer 115 arranged on the first feedback controller 110_1 side drives the first high-side transistor MH1 based on the control pulse S_H1. The buffer 116 arranged on the first feedback controller 110_1 side drives the first low-side transistor ML1 based on the control pulse S_L1. In the second mode, the third control signal S_CTRL3 including the replicas of the control pulses S_H1 and S_L1 is supplied to the second feedback controller 110_2 via the signal path 102.

In order to prevent through current from passing through the first high-side transistor MH1 and the second high-side transistor MH2, the control logic 113 monitors a signal that occurs at an internal node of the buffer 116. With this, during a period in which the first low-side transistor ML1 is instructed to be turned on, the control pulse S_H1 is fixedly set to the off level. Similarly, the control logic 114 monitors a signal that occurs at an internal node of the buffer 115. With this, during a period in which the first high-side transistor MH1 is instructed to be turned on, the control pulse S_L1 is fixedly set to the off level.

In the second mode, in order to provide dead-time control, the gate signal V_GH2 of the second high-side transistor MH2 and the gate signal V_GL2 of the second low-side transistor ML2 are supplied as a fourth control signal S_CTRL4 to the first feedback controller 110_1.