The second feedback controller 110_2 has the same configuration as that of the first feedback controller 100_1. In the first mode, the second feedback controller 110_2 operates in the same manner as the first feedback controller 110_1. However, in the second mode, the dead-time controllers 111 and 112 and the control logics 113 and 114 are stopped. In the second mode, the control signal S_CTRL3 including the control pulses S_H1 and S_L1 is supplied from the first feedback controller 110_1 to the second feedback controller 110_2. In the second mode, the buffer 115 drives the second high-side transistor MH2 based on the control pulse S_H1. Furthermore, the buffer 116 drives the second low-side transistor ML2 based on the control pulse S_L1.

It can be understood by those skilled in this art that the configuration of the feedback controller 110 is not restricted to such an example shown in FIG. 5.

FIG. 6A and FIG. 6B are circuit diagrams each showing an overcurrent protection circuit. FIG. 6A shows a state in the first mode, and FIG. 6B shows a state in the second mode. The first circuit block BLK1 and the second circuit block BLK2 each include a first overcurrent detection circuit 150_1 and a second overcurrent detection circuit 150_2.